Semiconductor Memory Interleave Address Conversion Circuit
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Solution Overview
Problem
Conventional NAND type flash memory interleave operations are hindered by the need for a dummy clock signal when accessing memory cores at different sides, which complicates the circuit configuration and reduces operation speed.
Innovation Solution
The semiconductor memory device employs address conversion circuits that handle interleave operations by either outputting logical address data unchanged or adding a value to it, eliminating the need for a dummy clock signal, thus simplifying the circuit configuration and enhancing operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a dummy clock signal is used to handle interleave operations in conventional NAND type flash memory, then the memory can access multiple memory cores, but the circuit configuration becomes complex and operation speed is reduced
Solution Approach 1:
The patent extracts and eliminates the dummy clock signal from the interleave operation system. By removing this unnecessary signal component, the circuit configuration is simplified while the interleave operation capability is maintained through alternative address conversion mechanisms in the column control circuits.
Solution Approach 2:
The column control circuits are designed to perform multiple functions: they handle both normal sequential operations and interleave operations using the same basic circuit structure. The address conversion circuits within the column control circuits can dynamically adjust their behavior based on the operation type, eliminating the need for separate dummy clock signal generation circuits.
2Adaptability or versatility
If a dummy clock signal is used to handle interleave operations, then memory cores can be accessed alternately, but the operation speed is reduced
Solution Approach 1:
By removing the dummy clock signal from the system, the patent eliminates the timing delays and signal propagation overhead associated with generating and synchronizing this unnecessary clock signal. The interleave operations proceed using the existing clock signals without the additional timing complexity, thereby improving operation speed.
3Adaptability or versatility
If address conversion is always performed in the column control circuit, then interleave operations can be handled, but the circuit complexity increases
Solution Approach 1:
The address conversion function in the column control circuits is made dynamic rather than static. The circuits can adaptively switch between performing address conversion and passing through addresses unchanged, depending on whether an interleave operation is required. This dynamic behavior allows the same circuit to handle both interleave and normal operations without requiring separate dedicated circuits for each function.
Data Source
AI summary
A plurality of address conversion circuits are provided for memory cores respectively, and convert logical address data supplied from outside to physical address data. In an interleave operation, the address conversion circuits output the logical address data as the physical address data without converting the logical address data when a first memory core is to be accessed earlier than a second memory core, whereas output address data obtained by adding a certain value to the logical address data as the physical address data when the second memory core is to be accessed earlier than the first memory core.