Memory Interleaving Across Multiple Chips to Cut Transfer Delays
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Solution Overview
Problem
Memory systems experience degraded data transfer performance due to longer data transfer times from memory cell arrays to page buffers compared to page buffers to controllers, especially in multi-level cell memory devices as memory capacity increases.
Innovation Solution
A memory system with a controller that independently accesses multiple memory devices via channels with input/output data lines and chip enable signal lines, allowing simultaneous read or program operations across devices, and an error correcting code block for error detection and correction, operating in a pipeline mode to enhance data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer is performed sequentially from memory cell array to page buffer to controller, then data integrity is maintained, but data transfer performance is degraded due to longer transfer time from memory cell array to page buffer
Solution Approach 1:
The patent divides the data transfer process into multiple independent segments by introducing multiple memory devices (first memory device, second memory device, etc.) that can operate simultaneously. Each memory device has its own page buffer and can transfer data to the controller in parallel, segmenting the overall transfer process to reduce total transfer time while maintaining integrity through sequential access control.
Solution Approach 2:
The patent transitions from a single-dimensional sequential transfer approach to a multi-dimensional parallel transfer approach by adding multiple memory devices and their associated page buffers. This dimensional expansion allows simultaneous data transfer operations across different memory devices, effectively reducing the bottleneck caused by sequential transfer from memory cell array to page buffer.
2Productivity
If multiple memory devices are accessed simultaneously to improve data transfer performance, then standby time is reduced, but control complexity increases due to multiple chip enable signal lines
Solution Approach 1:
The controller is designed with multi-functional capability to manage multiple memory devices through standardized control mechanisms. The chip enable signal lines, while multiple in number, follow a uniform control pattern where each line independently enables its associated memory device. This universal control approach allows the controller to efficiently manage parallel access to multiple devices without proportionally increasing control complexity.
Data Source
AI summary
A memory system includes a plurality of memory devices, a controller configured to control the plurality of memory devices, and at least one channel connected between the plurality of memory devices and the controller. The at least one channel includes input/output data lines and control signal lines, which are connected with the plurality of memory devices, and chip enable signal lines respectively connected to each of the plurality of memory devices, wherein the chip enable signal lines enable the plurality of memory devices independently. The controller sends a read command or a program command to one of the plurality of memory devices, and while the one of the plurality of memory devices is performing an internal read operation in response to the read command, the controller reads data from another one of the plurality of memory devices, or while the one of the plurality of memory devices is performing an internal program operation in response to the program command, the controller programs data to another one of the plurality of memory devices.