Semiconductor Memory I/O Architecture for HCB Full-Duplex Access
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Solution Overview
Problem
Existing semiconductor memory devices face limitations in utilizing the advantages of hybrid copper bonding (HCB) and advanced packaging methods for high-speed connection between chips, particularly in signal transmission paths, leading to challenges in reducing latency and increasing bandwidth.
Innovation Solution
A semiconductor memory device employing hybrid copper bonding (HCB) for direct electrical connection of chips without micro bumps, enabling simultaneous read and write operations through independent data paths and eliminating serialization and deserialization processes, thereby optimizing throttling delay times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If micro bumps are used for electrical connection between chips, then connection reliability is improved, but signal transmission path length cannot be sufficiently shortened
Solution Approach 1:
The patent extracts and removes the micro bump structure from the connection system, replacing it with direct wire bonding between chips. This eliminates the intermediate connection element (micro bump) that limited signal transmission path shortening while maintaining connection reliability through direct bonding interfaces.
Solution Approach 2:
The patent introduces an advanced packaging structure as an intermediary that enables direct wire bonding between chips. This packaging structure provides the necessary mechanical support and alignment features to achieve direct connections without micro bumps, thereby shortening the signal transmission path while maintaining reliability.
2Length of moving object
If hybrid copper bonding HCB is applied for electrical connection without micro bumps, then signal transmission path is shortened, but advantages of HCB and advanced packaging methods cannot be fully utilized in existing input/output structure
Solution Approach 1:
The patent segments the data transmission path into independent parallel channels, allowing simultaneous read and write operations through separate input/output structures. This segmentation enables the full utilization of HCB advantages by providing dedicated paths that can operate independently at high speeds without interference.
Solution Approach 2:
The patent transitions from sequential single-data-rate operations to parallel double-data-rate operations by utilizing the spatial dimension of multiple independent data paths. This dimensional change allows simultaneous read and write operations, fully exploiting the short signal transmission path enabled by HCB.
3Reliability
If serialization and deserialization processing is used for data transmission, then data integrity is improved, but data input/output latency increases
Solution Approach 1:
The patent extracts and removes the serialization and deserialization processing stages from the data transmission path. By using direct parallel data paths with independent input/output structures, the system maintains data integrity through dedicated signaling while eliminating the time-consuming serialization/deserialization conversion processes.
Solution Approach 2:
The patent skips the intermediate serialization and deserialization steps by implementing direct parallel data transmission. Data is transmitted directly through independent input/output structures without being converted to serial form, thereby rushing through the transmission process with minimal latency while maintaining integrity through dedicated signal paths.
4Ease of manufacture
If conventional packaging methods are used, then manufacturing simplicity is maintained, but bandwidth and power efficiency cannot be optimized
Solution Approach 1:
The patent merges multiple functionality into the advanced packaging structure, which simultaneously provides mechanical support, electrical connection, alignment features, and enables parallel data paths. This integration achieves high bandwidth and power efficiency while maintaining manufacturing simplicity by consolidating multiple functions into a single packaging solution rather than requiring separate components.
Data Source
AI summary
A semiconductor memory device, includes, a cell array including a plurality of memory banks, a command decoder configured to decode a read/write command, a read command, and a write command that are input from outside of the semiconductor memory devide, an address decoder receiving a read address and a write address, an input receiver configured to transmit write data input through a write data pad to a global input/output driver of a memory bank corresponding to the write address, and an output driver configured to transmit read data output from an input/output sense amplifier of a memory bank corresponding to the read address to a read data pad, wherein the write data is input via the write data pad in a single data rate method and transmitted to the global input/output driver without deserialization processing, and the read data is transmitted from the input/output sense amplifier to the read data pad without serialization processing. In some embodiments, the semiconductor memory device is electrically and physically coupled to a central processing unit by hybrid copper bonding.