Memory Chip I/O Mapping to Cut Signal Lines and Routing Complexity
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Solution Overview
Problem
As the number of memory chips increases in a memory device, the complexity of interconnection between the memory controller and the chips increases, leading to difficulties in routing and signal delays.
Innovation Solution
Implementing an input/output mapping connection method that allows memory chips to selectively ignore input/output signals from the memory controller, reducing the number of signal lines and enabling independent control of each chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory chips increases, then the storage capacity increases, but the number of signal lines increases and interconnection becomes complicated
Solution Approach 1:
Multiple memory chips share common input/output signal lines through a mapping connection mechanism. The chips are grouped and share signal lines within each group, reducing the total number of signal lines required. This merging approach allows multiple chips to communicate through shared resources rather than requiring dedicated lines for each chip.
Solution Approach 2:
The input/output signal lines serve multiple functions by being shared across multiple memory chips through the mapping connection. A single signal line can be dynamically assigned to different chips based on the active group, making the signal lines universal rather than dedicated to specific chips.
2Quantity of substance
If the number of memory chips increases, then the storage capacity increases, but routing difficulty increases
Solution Approach 1:
The memory device is segmented into multiple groups of memory chips, where each group shares a set of input/output signal lines. This segmentation allows for modular routing design, where signal lines are routed to groups rather than individually to each chip, significantly reducing routing complexity and manufacturing difficulty.
3Quantity of substance
If the number of memory chips increases, then the storage capacity increases, but signal delay increases
Solution Approach 1:
A group selection signal mechanism acts as an intermediary to manage communication between the memory controller and multiple memory chip groups. The group selection signal quickly switches which group is active, enabling rapid signal routing without requiring complex multi-path signal distribution, thereby reducing signal delay.
Data Source
AI summary
Disclosed is a memory system including a memory device and a memory controller. The memory device includes a package of a first memory chip configured to receive input/output signals through first input/output pads and a second memory chip having second input/output pads connected to the first input/output pads by a mapping connection. The memory controller configured to provide the input/output signals to the memory device. The second memory chip is configured to receive input/output signals different from the input/output signals provided by the memory controller to the first memory chip due to the mapping connection. The first and second memory chips are configured to selectively ignore the input/output signals provided by the memory controller based on the mapping connection.