Memory I/O Pin Capacitance Reduction via Slit Channels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Parasitic capacitance in memory devices, caused by the proximity of polysilicon layers to via structures, leads to decreased performance by limiting communication bandwidth due to high capacitance on I/O pins.
Innovation Solution
The formation of slit channels or staircase channels through the tier of polysilicon and dielectric layers around vias, which isolates the polysilicon layers and reduces parasitic capacitance by segmenting it into series capacitances, thereby improving I/O pin performance without adding extra cost or time to the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If polysilicon layers are placed close to via structures for compact design, then device integration density is improved, but parasitic capacitance increases and communication bandwidth decreases
Solution Approach 1:
The patent introduces slit channels that segment the polysilicon layers into isolated regions around the via structure. This segmentation breaks the continuous capacitive coupling between polysilicon layers and the via, effectively reducing parasitic capacitance while maintaining the compact layout for high integration density
2Reliability
If polysilicon layers are isolated from vias using slit channels, then parasitic capacitance is reduced and communication bandwidth is improved, but fabrication process complexity increases
Solution Approach 1:
The patent combines the formation of slit channels with existing fabrication processes by integrating them into the same etching and deposition sequences used for creating memory structures. This merging approach reduces the need for separate dedicated process steps, thereby limiting the increase in fabrication complexity while achieving effective polysilicon isolation
3Reliability
If slit channels are formed around vias to reduce parasitic capacitance, then I/O pin performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies slit channels selectively only around specific via structures where parasitic capacitance is most critical, rather than uniformly across the entire device. This localized application focuses manufacturing precision requirements on specific high-impact areas while maintaining tolerance in other regions, thereby improving I/O performance without uniformly increasing precision demands across the whole fabrication process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduction in parasitic capacitance enhances the communication bandwidth of memory devices by effectively isolating the polysilicon layers, improving the performance of I/O pins without introducing additional processing steps or materials.
Implementation Method 1
Parasitic capacitance in memory devices, caused by the proximity of polysilicon layers to via structures, leads to decreased performance by limiting communication bandwidth due to high capacitance on I/O pins
Data Source
AI summary
In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.