Semiconductor Memory Isolation Layer Formation
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Solution Overview
Problem
As semiconductor memory devices integrate more densely, the formation of isolation layers becomes challenging due to increased trench aspect ratios, leading to voids and seams that cause electrical degradation and etch damage, particularly due to the presence of fluorine-containing impurities.
Innovation Solution
A method involving gap-filling the trench bottoms with a first dielectric layer, followed by a dry etch process using a mixed gas of NH3 and HF, and subsequent annealing, then a wet etch process to remove fluorine-containing impurities, while widening the trench top width, ensuring the formation of dense dielectric layers to prevent electrical degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the trench aspect ratio is increased to accommodate higher degree of integration, then the isolation layer can be formed between narrower strings, but voids are generated within the trench and electrical characteristics degrade
Solution Approach 1:
The isolation layer formation is divided into multiple steps: first forming a liner dielectric layer to cover the trench bottom and prevent voids, then forming a main dielectric layer to complete the isolation. This segmentation of the dielectric layer formation process resolves the contradiction by addressing the void formation issue through staged deposition.
Solution Approach 2:
The liner dielectric layer is formed preliminarily before the main dielectric layer to prevent void formation in high aspect ratio trenches. This preliminary action ensures that the trench bottom is properly covered even when the aspect ratio is high, maintaining electrical characteristics while enabling narrower string formation.
2Manufacturing precision
If material with excellent step coverage is employed to gap-fill the trench, then the trench can be fully filled, but materials on the sidewalls face each other forming seams that cause etch damage
Solution Approach 1:
The harmful seam formation is eliminated by extracting the problematic condition of excessive material deposition. Instead of using material with excellent step coverage that causes seam formation, the process uses controlled deposition to fill the trench without creating overlapping sidewall materials, thus preventing etch damage while maintaining adequate gap-fill quality.
Solution Approach 2:
The potential harm of seam formation is converted into benefit by using a controlled deposition process that fills the trench adequately without creating seams. The liner dielectric layer provides just enough coverage to prevent voids without excessive deposition that would create harmful seams on the sidewalls.
3Ease of manufacture
If a wet etch process is performed to widen the trench top width, then the etch rate can be controlled, but fluorine-containing impurities are generated that lower program threshold voltage
Solution Approach 1:
The wet etch process is replaced with a dry etch process to widen the trench top width. This substitution eliminates the generation of fluorine-containing impurities that occur with wet etching, while still achieving the desired trench widening effect through controlled dry etching parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces fluorine-containing impurities and prevents electrical degradation, ensuring improved electrical characteristics and reliability of semiconductor memory devices by uniformly widening the trench and removing surface impurities.
Implementation Method 1
a first dielectric layer and a second dielectric layer are formed within a trench
Implementation Method 2
a first dielectric layer and a second dielectric layer are formed within a trench
Implementation Method 3
performing a dry etch process and a wet etch process
Implementation Method 4
annealing, by which fluorine-containing impurities formed in the first dielectric layer as a result of the first etch process and the annealing process are removed
Implementation Method 5
performing a dry etch process and a wet etch process
Data Source
AI summary
A method of forming isolation layers of a semiconductor memory device. In accordance with an embodiment of the invention, a semiconductor substrate in which trenches are formed is provided. A first dielectric layer is formed over the semiconductor substrate including the trenches. An opening width of the trench is widened by performing a first etch process to remove a part of the first dielectric layer, followed by an annealing process. Fluorine-containing impurities formed in the first dielectric layer as a result of the etching and annealing processes are removed by performing a second etch process. A second dielectric layer is formed over the semiconductor substrate including the first dielectric layer.