Memory Latch Circuit With Pre-Charge Gating for Lower Power
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines within these digital devices changes, affecting operating voltages and overall IC performance.
Innovation Solution
A memory circuit design that includes a NAND logic gate, N-type transistors, inverters, and a latch, where the first N-type transistor is coupled between the second N-type transistor and the voltage supply node of the NAND logic gate, allowing the NAND logic gate circuit to be disabled in response to a pre-charge signal, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the memory circuit uses conventional transistor configurations, then the circuit can operate reliably, but the power consumption increases due to more toggling transistors
Solution Approach 1:
The patent extracts and removes unnecessary transistors from the conventional memory circuit configuration. By taking out redundant transistors that do not contribute to essential circuit functions, the design reduces the total number of toggling transistors, thereby lowering power consumption while preserving the core operational reliability of the memory circuit.
Solution Approach 2:
The patent implements dynamic control of transistor switching through optimized clock signal phases and pre-charge signals. By dynamically managing which transistors are active at different times during the memory operation cycle, the circuit minimizes simultaneous toggling events, reducing power consumption while maintaining reliable data storage and retrieval operations.
2Use of energy by moving object
If the memory circuit reduces the number of transistors to lower power consumption, then energy efficiency improves, but the device complexity may increase due to optimized transistor coupling
Solution Approach 1:
The patent merges multiple transistor functions into fewer optimized transistor units. By combining the roles of storage, switching, and control functions into a reduced set of carefully coupled transistors, the design achieves lower power consumption while the apparent complexity is managed through functional integration rather than proliferation of separate components.
Solution Approach 2:
The remaining transistors in the optimized circuit are designed to perform multiple functions simultaneously. Each transistor is configured to participate in various circuit operations including data storage, signal amplification, and control logic, thereby reducing the total transistor count needed while maintaining full circuit functionality and reducing overall power consumption.
Data Source
AI summary
A memory circuit includes a NAND logic gate configured to generate a first signal responsive to at least one of a first bit line signal or a second bit line signal, a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal, a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal, and a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to an inverted first pre-charge signal. The inverted first pre-charge signal is inverted from the first pre-charge signal.