Semiconductor Memory Layer Structure for Electric Flux Uniformity
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Solution Overview
Problem
Current semiconductor memory devices face challenges in optimizing the configuration of conductive layers and gate insulating films, leading to variations in electric flux density and memory cell characteristics due to differences in surface shapes and material compositions, which affect storage and retrieval of data.
Innovation Solution
The semiconductor memory device incorporates conductive layers with varying surface shapes and compositions, such as straight and recessed surfaces, and adjusts the silicon-to-nitrogen ratio in insulating layers to form desired curved surfaces, optimizing the interaction between conductive layers and semiconductor layers to enhance electric flux density and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive layers are used with uniform structure and material composition, then manufacturing is simplified, but electric flux density varies across different levels leading to inconsistent memory cell characteristics
Solution Approach 1:
The patent applies local quality by varying the silicon and nitrogen ratios in different regions of the conductive layers. Specifically, the conductive layers have different compositions at different heights (first conductive layer has different Si/N ratio than second conductive layer), allowing each region to optimize electric flux density locally while maintaining overall device functionality.
Solution Approach 2:
The patent changes material composition parameters (silicon and nitrogen ratios) to control electric flux density. By adjusting these compositional parameters across different conductive layers and regions, the patent optimizes charge storage characteristics and reduces variations in memory cell performance.
2Reliability
If conventional conductive layer structures are used, then manufacturing processes are simpler, but leakage currents increase due to insufficient electric flux density control
Solution Approach 1:
The patent utilizes Chemical Vapor Deposition (CVD) processes to precisely control silicon and nitrogen ratios in the conductive layers. By adjusting deposition parameters and recipe conditions, the patent achieves optimal material composition that reduces leakage currents while managing manufacturing complexity.
Solution Approach 2:
The patent employs composite conductive layers with different material compositions (varying silicon and nitrogen ratios) in different regions. These composite structures enable optimized electric flux density distribution and reduced leakage currents by combining materials with different electrical properties.
3Manufacturing precision
If metal halides are used to control material distribution, then electric flux density uniformity improves, but process complexity increases
Solution Approach 1:
The patent employs metal halides as catalysts or additives in the CVD process to control the distribution of silicon and nitrogen in the conductive layers. By adjusting metal halide concentration and deposition conditions, the patent achieves uniform electric flux density while managing process complexity through controlled parameter changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the consistency and performance of memory cells by optimizing electric flux density and reducing variations in characteristics, thereby enhancing data storage and retrieval efficiency.
Implementation Method 1
using methods like Chemical Vapor Deposition (CVD) and Reactive Ion Etching (RIE) to form conductive layers with specific silicon and nitrogen ratios
Implementation Method 2
using methods like Chemical Vapor Deposition (CVD) and Reactive Ion Etching (RIE) to form conductive layers with specific silicon and nitrogen ratios
Implementation Method 3
employing metal halides to control material distribution
Data Source
AI summary
A semiconductor memory device includes conductive layers, a semiconductor layer opposed to the conductive layers, and a gate insulating film disposed therebetween. When positions corresponding to surfaces on one and the other sides of the first conductive layer and an intermediate position thereof are respectively assumed to be a first position to a third position, when positions corresponding to surfaces on one and the other sides of the second conductive layer and an intermediate position thereof are respectively assumed to be a fourth position to a sixth position, and when lengths of the semiconductor layer at the first position to the sixth position are respectively assumed to be a first length to a sixth length, the first length to the third length are smaller than the fourth length to the sixth length, and the third length is smaller than the first length and the second length.