Memory Layout Verification Circuit for Bit and Word Line Order
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Solution Overview
Problem
Verifying the correct order of bit lines and word lines in memory layouts is cumbersome and time-consuming, as existing tools like LVS do not effectively identify or locate order mismatches, leading to potential faults in memory built-in self-tests.
Innovation Solution
Incorporating stacked transistors that introduce asymmetry to break symmetry in bit line and word line arrangements, allowing layout versus schematic checks to easily identify and correct order mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional layout verification tools are used, then memory layout can be verified, but the process is cumbersome and time-consuming
Solution Approach 1:
The memory device performs self-verification by incorporating verification transistors and logic gates directly into the memory structure. The circuit automatically checks bit line and word line ordering during manufacturing without requiring external manual verification tools, making the system self-sufficient for quality control.
Solution Approach 2:
The verification circuit is built into the memory during the manufacturing process, performing verification actions before the memory is delivered to the customer. This preliminary verification ensures that any ordering errors are caught early, eliminating the need for time-consuming post-manufacturing checks.
2Ease of manufacture
If symmetry is maintained in bit line and word line arrangements, then memory layout is simplified, but order mismatches become difficult to detect
Solution Approach 1:
The verification circuit introduces asymmetric elements (verification transistors with specific gate connections, logic gates with fixed input/output configurations) into the otherwise symmetric memory layout. These asymmetric verification structures create detectable patterns that reveal ordering errors, allowing the circuit to distinguish correct from incorrect configurations even in symmetric layouts.
3Reliability
If manual verification is performed, then verification can be conducted, but time and cost increase
Solution Approach 1:
The memory device performs self-verification by incorporating verification transistors and logic gates directly into the memory structure. The circuit automatically checks bit line and word line ordering during manufacturing without requiring external manual verification tools, making the system self-sufficient for quality control.
Solution Approach 2:
The patent replaces manual verification processes with an automated electrical verification circuit. Instead of requiring human operators to visually inspect and manually check layout files, the electronic verification circuit uses electrical signals to automatically detect ordering errors, substituting mechanical/manual verification with electronic automation.
Data Source
AI summary
A memory is provided with a stack of word line transistors for verifying a word line order and with a stack of bit line transistors for verifying a bit line order. The stack of word line transistors couple between the output terminals of a row decoder and a plurality of word lines. Similarly, the stack of bit line transistors couple between the output terminals of a column multiplexer and a plurality of bit lines.