Memory Leakage Controller for Over-Erased Cell Recovery
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Solution Overview
Problem
Over-erased memory cells in non-volatile semiconductor devices can lead to background current leakage due to abnormal power loss, causing incorrect data reading during memory operations.
Innovation Solution
A method and controller for recovering over-erased memory cells by checking bit line leakage during power-on procedures or in response to user commands, using leakage detection and recovery programming to eliminate background leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase operation is performed on memory cells, then memory capacity is cleared, but over-erase may occur causing background current leakage
Solution Approach 1:
The patent performs leakage detection during the power-on procedure before any read or write operations. The leakage controller proactively identifies over-erased memory cells by detecting abnormal current on bit lines, and recovers them through soft-programming operations. This preliminary action prevents leakage-related errors from affecting subsequent memory operations.
Solution Approach 2:
The patent implements a feedback mechanism where the leakage controller continuously monitors bit line current during power-on and subsequent operations. When leakage is detected, the system automatically triggers soft-programming recovery operations on the affected memory cells, then re-verifies the leakage condition. This closed-loop feedback ensures that over-erased cells are identified and corrected, eliminating background current leakage while maintaining data accuracy.
2Reliability
If soft-programming operation is performed to recover over-erased cells, then leakage is reduced, but additional operation time is required
Solution Approach 1:
The patent performs leakage detection and recovery operations during the power-on procedure, which is a mandatory initialization step anyway. By integrating leakage recovery into this existing timeline rather than adding a separate operation, the patent minimizes additional time overhead while ensuring memory reliability before normal operations begin.
Solution Approach 2:
The patent applies soft-programming recovery only to memory cells that exhibit leakage symptoms, rather than re-programming the entire memory array. The leakage controller identifies specific bit lines with abnormal current and targets only the affected memory cells for recovery, significantly reducing the time required compared to a full memory recovery operation.
Data Source
AI summary
An operation method for a memory is provided. The operation method includes: starting a power on procedure on the memory; checking leakage for a bit line of the memory; and if the bit line has leakage, performing a leakage recovery on the bit line until the bit line passes the checking leakage step.