Unified Memory-Logic IC Layout Without Voltage Translation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing IC systems for high-performance computing and AI face challenges due to the incompatibility of supply voltages between DRAM chips and logic chips, leading to difficulties in energy efficiency and performance synchronization. Additionally, the DRAM technology scaling has slowed down, making it hard to achieve sub-10 nanometer process nodes, and the memory-wall effect reduces data transfer rates between logic and memory.
Innovation Solution
The proposed IC system includes a package with a logic chip and a plurality of memory dies, where each memory die has a memory region with 3D structured transistors and a bridge area with additional transistors. The logic chip is physically separated from the memory dies but configured within the same package, with the memory I/O pads electrically coupled to the logic I/O pads without additional voltage conversion circuits, ensuring compatible voltage levels and eliminating the need for voltage translation circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM technology uses stacked capacitor structure after transistor formation, then capacitor integration is achieved, but transistor scaling and leakage control are compromised
Solution Approach 1:
The patent segments the DRAM cell structure into separate components: the access transistor is formed in the substrate with source and drain regions, while the capacitor is implemented as a stacked capacitor structure formed in a separate region. This segmentation allows independent optimization of transistor scaling and capacitor integration, resolving the conflict between achieving capacitor integration and maintaining transistor scaling precision.
2Reliability
If 3D transistor structures are used in logic chips, then performance and leakage control are improved, but supply voltage compatibility with DRAM chips becomes problematic
Solution Approach 1:
The patent introduces an intermediary mechanism through the unified IC system architecture where the DRAM chip and logic chip are integrated on the same substrate. The system includes voltage regulation circuits and level shifters that act as intermediaries to translate between the 1.2V DRAM voltage domain and the lower voltage logic domain, enabling voltage compatibility while preserving the leakage control benefits of 3D transistor structures.
3Speed
If DRAM and logic chips are integrated in the same package, then data transfer rate is improved, but voltage level incompatibility requires additional conversion circuits
Solution Approach 1:
The patent merges the DRAM chip and logic chip into a unified IC system where both are integrated on the same substrate with shared power domains. By combining the voltage regulation and level shifting functions directly within the integrated structure rather than as separate external circuits, the system achieves high data transfer rates while minimizing the complexity of voltage conversion through shared infrastructure.
Data Source
AI summary
An IC system includes a package, a plurality of memory dies, and a logic chip. The plurality of memory dies are within the package, each memory die includes a memory region and abridge area, the memory region of each memory die includes a plurality of memory cells and each memory cell includes a first transistor, and the bridge area of each memory die includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The logic chip includes a logic bridge area and a plurality of second transistors, and the logic bridge area includes a plurality of logic I/O pads. Each memory die is horizontally spaced apart from the logic chip, and the plurality of memory I/O pads of each memory die are electrically coupled to the plurality of logic I/O pads. Each memory die is horizontally spaced apart from each other.