Memory Mat Edge Structure Using Layer-Separated Moat Isolation
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high data reliability, high speed of memory access, low power consumption, and reduced chip size, particularly due to issues with the formation of memory mat edges that can lead to shorts and defects during manufacturing.
Innovation Solution
The implementation of a memory mat edge structure with a moat structure in a layer different from the redistribution layer (RDL) structures, avoiding double etching and reducing the likelihood of shorts, while maintaining reliability and efficiency in data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the moat structure is formed in the same layer as the RDL structures, then the manufacturing process is simplified, but shorts and defects occur during manufacturing
Solution Approach 1:
The patent resolves the contradiction by moving the moat structure from the same layer as the RDL structures to a different layer (either above or below). This dimensional separation in the layer stack allows the moat structure to serve its isolation function without interfering with the RDL structures, thereby preventing shorts while maintaining manufacturability through controlled layer formation processes.
Solution Approach 2:
The patent applies segmentation by separating the moat structure formation into a distinct layer from the RDL structures. This layer segmentation enables independent formation and control of each structure, allowing the moat to be created as a separate entity that isolates memory mat edges without conflicting with the RDL network, thus preventing shorts while maintaining ease of manufacture through modular processing.
2Manufacturing precision
If double etching is used to form the memory mat edge structure, then manufacturing precision is improved, but the likelihood of shorts increases
Solution Approach 1:
The patent resolves this contradiction by forming the memory mat edge structure in a different layer from the RDL structures. This layer separation maintains manufacturing precision through controlled etching processes while preventing shorts by ensuring that the precisely formed edge structures do not come into contact with conductive RDL structures in adjacent layers.
Solution Approach 2:
The patent introduces an intermediary layer separation between the memory mat edge structure and the RDL structures. This intermediate layer acts as an insulator that allows precise formation of the edge structure through etching while preventing direct contact and potential shorts with the conductive RDL network in other layers.
3Reliability
If the moat structure is separated from the RDL structures into a different layer, then shorts are prevented, but device complexity increases
Solution Approach 1:
The patent accepts the increased device complexity in the vertical dimension (additional layers) as necessary to achieve the primary goal of short prevention. The layer separation creates a three-dimensional structure that isolates conductive elements, and this complexity is managed through standard semiconductor manufacturing processes that form multiple layers in a controlled sequence.
Solution Approach 2:
The patent segments the device structure into distinct functional layers, with the moat structure in one layer and RDL structures in another. This segmentation increases structural complexity but enables independent optimization of each layer's function, allowing the moat to provide reliable isolation while the RDL layer provides conductive connectivity without interference.
Data Source
AI summary
Some embodiments of the disclosure provide an apparatus comprising a memory mat including a memory cell portion, a dummy portion adjacent to the memory cell portion, and an edge portion adjacent to the dummy portion. The memory cell portion includes a first capacitor structure, a first redistribution layer structure coupled to the first capacitor structure, and a cell contact structure coupled to the redistribution layer structure, and the first capacitor structure is coupled to the cell contact structure by the first redistribution layer structure. The dummy portion includes a second capacitor structure and a second redistribution layer structure coupled to the second capacitor structure. The edge portion includes an outermost capacitor structure and a conductive layer structure coupled to the outermost capacitor structure, and the conductive layer structure is at a position higher than the first and second redistribution layer structures on the semiconductor substrate.