Memory Module Layered DQ Routing to Reduce Reference Changes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional dual-rank DIMM designs fail to address signal quality issues due to data signals being routed on the same layer, leading to numerous reference changes that negatively affect performance.
Innovation Solution
Data signals are routed on separate layers of the memory module, reducing the number of reference changes by transmitting even and odd DQ bits on different layers, with a memory controller ensuring they arrive at the memory chip simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data signals are routed on the same layer, then routing simplicity is maintained, but signal quality deteriorates due to numerous reference changes
Solution Approach 1:
The patent transitions from routing all data signals on a single layer to distributing them across multiple layers. Specifically, even DQ bits are routed on one layer while odd DQ bits are routed on a different layer, utilizing the vertical dimension (layer separation) to reduce reference changes and improve signal quality without significantly increasing routing complexity.
2Reliability
If data signals are routed on separate layers, then signal quality improves by reducing reference changes, but routing complexity increases
Solution Approach 1:
The patent segments the data signal routing into distinct groups based on bit position parity. Even DQ bits are assigned to one layer and odd DQ bits to another layer, creating segmented routing paths that reduce reference changes for each group while maintaining overall system functionality.
Solution Approach 2:
The patent utilizes the layer dimension to separate data signal routing, transitioning from a single-layer approach to a multi-layer approach. This dimensional change allows signals to maintain consistent references across longer paths while reducing the number of reference changes required, thereby improving signal quality.
3Reliability
If even and odd DQ bits are transmitted on different layers, then reference changes are reduced, but timing synchronization becomes more challenging
Solution Approach 1:
The patent employs parameter changes in routing configurations to compensate for the timing differences introduced by multi-layer routing. By adjusting routing parameters such as via locations, trace lengths, and layer assignments, the system achieves timing synchronization between signals from different layers without compromising signal quality benefits.
Data Source
AI summary
Apparatuses and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane.