Memory Module Pin Arrangement for Impedance Reduction
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Solution Overview
Problem
Conventional memory modules face issues such as noise on power lines, complex layout due to separate decoupling capacitors for core and I/O circuitry, increased impedance between power and ground pins, and reduced reliability due to a large number of pins, leading to inefficient performance and potential electrical connection issues.
Innovation Solution
The memory module design features a shared set of power pins for both core and I/O circuitry, with power pins placed adjacent to ground pins to reduce noise, and all signal pins referencing ground for reduced impedance, along with redundant address and control pins for enhanced reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two different sets of power pins are used for core circuitry and I/O circuitry, then proper power supply is achieved, but layout complexity increases and decoupling capacitors cannot be shared
Solution Approach 1:
The patent merges the power pin sets by making the first set of power pins serve dual purposes for both core circuitry and I/O circuitry. This consolidation allows a single set of decoupling capacitors to serve both circuit types, reducing layout complexity while maintaining proper power supply functionality through shared power delivery infrastructure.
2Device complexity
If power pins are spaced apart from ground pins by intervening signal pins, then pin arrangement is simplified, but impedance between power and ground pins increases leading to increased noise
Solution Approach 1:
The patent applies local quality by placing ground pins adjacent to power pins specifically at locations where signal pins would otherwise be positioned. This localized repositioning creates low-impedance return paths for power signals without requiring a complete redesign of the entire pin arrangement, thereby reducing noise while maintaining overall arrangement simplicity.
3Adaptability or versatility
If a large number of pins are provided on the memory module, then all signal connections are achieved, but reliability decreases due to increased likelihood of poor electrical connections
Solution Approach 1:
The patent implements multi-functionality by designing signal pins to serve dual purposes: some signal pins are configured to function as both signal carriers and ground references. This allows the memory module to maintain comprehensive signal connection capability while reducing the total number of pins required, thereby improving reliability by reducing the statistical likelihood of poor electrical connections.
Data Source
AI summary
A memory module according to one implementation includes a support substrate, plural memory devices mounted on the support substrate, and pins having a predetermined arrangement on the support substrate, the pins comprising signal pins connected to the memory devices, power pins, and ground pins. In the predetermined arrangement of pins, each signal pin uses a ground pin as a reference, and each power pin is adjacent a ground pin for reduced impedance between the power pin and ground pin. In some implementations, some of the signal pins are associated with redundant pins.