Memory Module Reset Controller Using PWM Time-Multiplexing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing sideband bus interface in memory modules lacks a dedicated reset signal, leading to unrecoverable conditions when the sideband bus control circuitry becomes stuck, resulting in data loss and downtime, as traditional reset methods are ineffective and require a system power cycle.
Innovation Solution
A memory module management controller with a reset controller that uses Pulse Width Modulation (PWM) to time-multiplex reset signals for the sideband bus control circuitry and other components, allowing for deterministic and isolated power-down resets without a dedicated reset pin, enabling recovery without a complete system power cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the sideband bus interface lacks a dedicated reset signal to simplify the interface design, then the device complexity is reduced, but the reliability deteriorates when the control circuitry becomes stuck
Solution Approach 1:
The patent combines the reset functionality with existing power management signals (PM_RSTB and PM_PWROK) that already control power states in the memory module. By merging the reset function into these existing signal pathways, the invention avoids adding dedicated reset pins or separate reset circuitry, thereby maintaining interface simplicity while enabling reliable reset capability through power state transitions.
Solution Approach 2:
The patent introduces a management controller as an intermediary that monitors the sideband bus control circuitry and triggers power state transitions when stuck conditions are detected. This intermediary component enables indirect reset functionality by mediating between the power management signals and the control circuitry, allowing recovery without direct reset signal wiring.
2Device complexity
If traditional reset methods are used without dedicated reset signals, then the device complexity remains low, but the loss of time increases due to required system power cycles
Solution Approach 1:
The patent segments the power management into distinct controllable states (off, standby, idle, active) with dedicated transition signals. By segmenting the power states and their control mechanisms, the system can perform targeted resets of specific components without requiring a complete system power cycle, thereby reducing downtime while maintaining simple reset architecture.
Solution Approach 2:
The patent implements preliminary power-down actions through controlled transitions to standby or idle states before attempting recovery operations. This preliminary action allows the system to prepare for reset by gradually reducing power states, enabling faster recovery compared to abrupt full power cycles while keeping the reset architecture simple.
3Reliability
If the sideband bus control circuitry is reset through power-down signals, then the reliability of reset functionality is improved, but the use of energy increases during reset operations
Solution Approach 1:
The patent employs periodic power state transitions rather than continuous power application during reset operations. By using timed transitions between power states (e.g., brief power-down followed by recovery), the system achieves reliable reset functionality while minimizing energy consumption compared to sustained high-power reset methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides hardware fault recovery and prevents data loss by enabling deterministic resets of the sideband bus control circuitry and other components, reducing downtime and eliminating the need for a system power cycle.
Implementation Method 1
A memory module management controller with a reset controller that uses Pulse Width Modulation (PWM) to time-multiplex reset signals for the sideband bus control circuitry and other components
Data Source
AI summary
A memory module management controller in a memory module includes a reset controller that monitors a reset signal received from a host memory controller in the host system that is communicatively coupled to the memory module. The memory module management controller includes sideband bus control circuitry. The memory module also includes memory integrated circuits (for example, Dynamic Random Access Memory (DRAM)) and a Registering Clock Driver (RCD). The reset signal from the host memory controller can be time multiplexed, a short duration pulse to indicate reset of the sideband bus control circuitry and a long duration pulse to indicate reset of other components in the memory module, for example, memory integrated circuits and/or Registering Clock Driver (RCD).