Memory System MSR Counters for Proactive Erroneous Bit Discovery
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Solution Overview
Problem
Existing memory systems face challenges in identifying and managing erroneous bits, which can lead to unreliable code words beyond the error recovery capability of the memory system, affecting system reliability and performance.
Innovation Solution
Implementing a memory system with Minimum Substitution Regions (MSRs) that include counters to track erroneous bits, a controller for error control operations, and a non-volatile memory to preserve error status during power fluctuations, enabling background operations to correct or replace unreliable memory regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction operations are performed on code words with excessive erroneous bits, then system reliability deteriorates, but if no error correction is performed, then data integrity is compromised
Solution Approach 1:
The system performs preliminary detection of erroneous bits in code words before attempting correction. By identifying the quantity of erroneous bits upfront, the system can determine whether correction is feasible, preventing wasted operations on irrecoverable data and maintaining both reliability and data integrity
Solution Approach 2:
The error detection and correction process incorporates feedback mechanisms where the quantity of erroneous bits is measured, compared against thresholds, and used to control subsequent correction operations. This feedback loop ensures that correction is only attempted when successful recovery is probable, balancing reliability preservation with data integrity maintenance
2Productivity
If background operations are implemented to discover erroneous bits, then productivity is improved, but device complexity increases
Solution Approach 1:
The memory system performs self-diagnosis through background operations that automatically discover and catalog erroneous bits without external intervention. This self-service capability improves productivity by proactively managing errors, while the automated nature minimizes the additional complexity required
Solution Approach 2:
Background operations perform preliminary discovery and mapping of erroneous bits before they affect normal operations. This advance preparation improves productivity by preventing future errors, while organizing error information in structured formats keeps the added complexity manageable
Data Source
AI summary
Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.