Memory Device Redesigning NC Terminals for Increased Functionality
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Solution Overview
Problem
The existing memory standards, such as JEDEC, restrict the number of functional terminals and no-connect (NC) terminals in memory devices, limiting the ability to increase functional terminals without compromising compatibility, which hinders the enhancement of memory chip performance and functionality.
Innovation Solution
Redesigning certain NC terminals to function as additional functional terminals, allowing them to connect to chip inputs/outputs, thereby increasing the number of functional terminals while maintaining compliance with memory standards by rerouting them to supply voltage, data, command, or address signals, or configuring them for test operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of functional terminals is increased to enhance memory chip performance and functionality, then the functionality and performance of the memory chip are improved, but the compatibility with existing JEDEC memory standards deteriorates
Solution Approach 1:
The patent applies multi-functionality by enabling NC terminals to serve dual purposes: they maintain their original role in standard compliance while simultaneously functioning as additional functional terminals. The NC terminals are configured to connect to internal circuits through redistribution layers, allowing them to transmit data signals, address signals, command signals, or power signals, thus increasing the effective number of functional terminals without changing the physical package terminal count.
Solution Approach 2:
The patent changes the electrical connection parameter of NC terminals from 'no connection' to 'connected to internal circuits'. By modifying the routing configuration in the package substrate, the NC terminals are reconfigured to establish electrical connections with specific chip I/Os, transforming them from inactive terminals to active functional terminals while maintaining the same physical package structure.
2Productivity
If additional functional terminals are added to the package, then the data bandwidth and storage capacity are extended, but the total number of package terminals exceeds JEDEC standard specifications
Solution Approach 1:
The patent enables existing NC terminals to perform additional functional roles beyond their original designation. By routing NC terminals to connect with internal circuitry through redistribution layers, the system extracts additional functional capacity from the existing package terminal infrastructure, thereby increasing data bandwidth and storage capacity without adding physical terminals.
Solution Approach 2:
The patent creates functional equivalents by routing NC terminals to mirror the functionality of existing functional terminals. The NC terminals are configured to carry similar signal types (data, address, command, power) as the original functional terminals, effectively creating additional signal pathways that replicate essential terminal functions without requiring physical duplication of terminals.
3Adaptability or versatility
If NC terminals are redesigned to connect to chip I/Os, then the number of functional terminals is increased, but the complexity of package substrate routing increases
Solution Approach 1:
The patent segments the routing function by introducing separate redistribution layers dedicated to connecting NC terminals to specific chip I/Os. Rather than creating complex point-to-point routes across the entire package substrate, the routing is divided into modular segments: the NC terminals connect to intermediate redistribution layers, which then connect to specific functional groups on the chip, simplifying the overall routing architecture.
Solution Approach 2:
The patent introduces redistribution layers as intermediary structures between the NC terminals and the chip I/Os. These intermediary layers act as connection hubs that simplify the routing complexity by providing standardized connection points, allowing NC terminals to be connected to multiple different I/O configurations without requiring custom routing paths for each connection.
Data Source
AI summary
A memory device is provided. The memory device includes: a package substrate; a memory chip, with chip inputs/outputs (I/Os), and attached to the package substrate; and package terminals, disposed on the package substrate, and having: functional package terminals, connected to the chip I/Os; no-connect (NC) package terminals, arranged among the functional package terminals and not connected to any of the chip I/Os; and redesigned NC package terminals, as additional ones of the NC package terminals but connected to the chip I/Os, so as to be functioned as additional functional package terminals.