Semiconductor Memory Output Buffer Impedance Calibration
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Solution Overview
Problem
Semiconductor devices, such as DRAM, face a trade-off between impedance-adjustment accuracy and calibration operation time due to the number of bits in the code signal used for impedance adjustment, making it difficult to achieve both high accuracy and high-speed operation.
Innovation Solution
A semiconductor device with a calibration circuit that generates a code signal to control transistors in the output buffer, allowing for impedance adjustment by converting a five-bit code signal to a seven-bit code signal, optimizing the number of selectable impedance values and calibration time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of bits in the code signal is increased to improve impedance-adjustment accuracy, then the impedance-adjustment accuracy is improved, but the calibration operation time increases
Solution Approach 1:
The calibration operation is divided into two phases: a first calibration operation that calibrates a first portion of the output buffer, and a second calibration operation that calibrates a second portion of the output buffer. This segmentation allows the calibration to be performed in stages, reducing the time penalty associated with using a multi-bit code signal while still achieving high impedance-adjustment accuracy through the combined effect of both calibration operations.
2Adaptability or versatility
If the number of bits in the code signal is increased to provide more selectable impedance values, then the adaptability is improved, but the device complexity increases
Solution Approach 1:
The output buffer is divided into a first portion and a second portion, each calibrated separately. The code signal is split into a first code signal for the first portion and a second code signal for the second portion. This segmentation reduces the complexity of the calibration circuit by breaking down the control of multiple transistors into manageable segments, while still providing a wide range of selectable impedance values through the combined calibration of both portions.
Solution Approach 2:
The calibration circuit dynamically selects which transistors to activate based on the code signal bits. The first calibration operation controls a first set of transistors in the first portion, while the second calibration operation controls a second set of transistors in the second portion. This dynamic control allows the system to achieve high adaptability with reduced circuit complexity by activating only the necessary components for each calibration stage.
Data Source
AI summary
A device includes a data output terminal, an output buffer including n first transistors (n is a natural number greater than 1) connected in parallel with the data output terminal, and a calibration circuit to output an n-bit first code signal for controlling each of the n first transistors. In some embodiments, the calibration circuit includes a first counter circuit to output a k-bit second code signal (k is a natural number less than n), and a first code conversion circuit to convert the k-bit second code signal to the n-bit first code signal. Additional apparatus, systems, and methods are disclosed.