Memory Output Circuit Drive Adjustment for Switching Noise

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Solution Overview

Problem

Semiconductor memory devices face challenges in stably outputting signals at high speeds due to the influence of simultaneous switching noise, which affects the drive capability of output circuits and can lead to incorrect data reading.

Innovation Solution

The implementation of an output control circuit that temporarily adjusts the drive capability of the output circuit by controlling the operation of pull-up and pull-down drivers in response to signal output, reducing the impact of simultaneous switching noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the output circuit operates at high speed to enable fast data transfer, then productivity is improved, but simultaneous switching noise increases causing signal instability

Engineering Contradiction:

Improvedata transfer speedVSAvoidsignal output stability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The control circuit performs preliminary action by adjusting the drive capability of the output circuit before simultaneous switching occurs. The control circuit detects when multiple output pins will switch simultaneously and pre-adjusts the drive capability to compensate for the upcoming noise, thereby maintaining signal stability during high-speed operation

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention changes the drive capability parameter of the output circuit dynamically based on the switching pattern of output pins. By adjusting the drive capability in response to detected simultaneous switching conditions, the system optimizes signal stability while maintaining high-speed data transfer performance

Inventive Principle:

Principle #35Parameter changes

2Reliability

If the drive capability is increased to maintain signal strength during simultaneous switching, then signal quality is improved, but noise interference increases affecting reading accuracy

Engineering Contradiction:

Improvesignal qualityVSAvoidnoise interference

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The control circuit applies local quality by adjusting the drive capability specifically for the output circuit during simultaneous switching events, rather than uniformly increasing drive capability for all outputs. This targeted adjustment maintains signal quality for affected pins while minimizing noise interference on other pins that are not simultaneously switching

Inventive Principle:

Principle #3Local quality

3Reliability

If the drive capability is temporarily adjusted to reduce noise impact, then signal stability is improved, but device complexity increases due to additional control circuitry

Engineering Contradiction:

Improvesignal output stabilityVSAvoidcontrol circuit structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The control circuit is designed with multi-functionality to minimize added complexity. It not only adjusts drive capability during simultaneous switching but also monitors output pin states, detects switching patterns, and manages timing for adjustments. This universal approach consolidates multiple functions into a single control unit rather than requiring separate circuits for each function

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12362020B2Semiconductor memory device having a control circuit for changing a drive capability of an output circuit of the semiconductor memory device

Publication Date: 2025.07.15 KIOXIA CORP

AI summary

A semiconductor memory device includes an output pin configured for connection with a memory controller, an output circuit configured to output through the output pin a voltage signal that changes over time in accordance with one or more bits of data to be output to the memory controller, and a control circuit configured to temporarily change a drive capability of the output circuit each time a voltage signal corresponding to one bit of the data is output through the output pin.