Nonvolatile Memory Device Oxygen Defect Control
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Solution Overview
Problem
Current nonvolatile semiconductor memory devices require high write voltages, typically 20 V or more, to vary the threshold voltages of memory cell transistors, which limits processing speed and increases chip area.
Innovation Solution
The device incorporates an oxide layer with controlled oxygen defect distribution between the gate insulating layer and the gate electrode, allowing threshold voltage variation with a write voltage of 10 V or less by moving oxygen defects with an electric field, reducing the need for high write voltages and enabling efficient data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high write voltage (20 V or more) is applied to vary threshold voltages of memory cell transistors, then data can be stored in nonvolatile semiconductor memory devices, but processing speed is limited and chip area increases
Solution Approach 1:
The patent changes the physical state and distribution of oxygen defects in the oxide layer by controlling formation conditions (temperature, atmosphere, time) to create a non-uniform oxygen defect distribution. This parameter change enables the oxide layer to achieve desired resistance variation with lower applied voltages (10 V or less), resolving the contradiction between reliable data storage and processing speed
Solution Approach 2:
The patent creates local quality differences by establishing a non-uniform oxygen defect distribution within the oxide layer, where different regions have different oxygen defect concentrations. This local variation in material properties allows the oxide layer to exhibit enhanced resistance change characteristics at lower voltages, improving processing speed while maintaining storage reliability
2Reliability
If high write voltage (20 V or more) is applied to vary threshold voltages of memory cell transistors, then data can be stored in nonvolatile semiconductor memory devices, but chip area increases
Solution Approach 1:
By changing the oxygen defect distribution parameters in the oxide layer during formation, the patent enables the memory device to achieve reliable data storage at lower operating voltages. This parameter optimization reduces the need for large voltage generation circuits and associated components, thereby reducing chip area while maintaining storage reliability
Solution Approach 2:
The patent uses the oxide layer's resistance change characteristics (caused by oxygen defect movement) as a copy mechanism to store data. Instead of requiring high-voltage charge injection into floating gates, the system copies information through resistance states, enabling more compact cell designs and reduced chip area
3Reliability
If high write voltage is applied, then threshold voltage can be varied for data storage, but write and erase times increase
Solution Approach 1:
The patent optimizes the oxygen defect distribution parameters in the oxide layer to enhance the speed of resistance change. By creating specific oxygen defect concentration gradients and utilizing their rapid movement in response to electric fields, the system achieves fast write and erase operations with reduced times while maintaining reliable data storage capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration lowers write and erase times, improves processing efficiency, and allows for high-capacity memory with reduced chip area, enabling storage of multiple bits based on threshold voltage levels.
Implementation Method 1
a plurality of first oxide layers 23 in which one side of the first oxide layers 23 is in contact with the plurality of second interconnect layers 14 while the other side of the first oxide layers 23 is in contact with the first insulating layer 12, and a voltage is applied to the plurality of second interconnect layers 14 to vary a resistance value of the plurality of first oxide layers 23
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a first interconnect layer provided above a semiconductor substrate; a plurality of second interconnect layers provided above the first interconnect layer; a semiconductor layer electrically coupled to the first interconnect layer; a first insulating layer provided between the semiconductor layer and the plurality of second interconnect layers; and a plurality of first oxide layers in which one side of the first oxide layers is in contact with the plurality of second interconnect layers while the other side of the first oxide layers is in contact with the first insulating layer, and a voltage is applied to the plurality of second interconnect layers to vary a resistance value.