Semiconductor Memory Pad Arrangement for Area Reduction
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Solution Overview
Problem
The size of pads in semiconductor memory devices has not corresponded to the increasing degree of integration, leading to overhead in chip size, particularly for low-integration memory devices, as manufacturing technology reduces chip size without reducing pad size.
Innovation Solution
The method involves classifying pads into monitoring, package, and common pads and arranging them in specific columns on the memory chip, with package pads being smaller than monitoring pads and all pads being used for both wafer testing and packaging, optimizing their placement to reduce area occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration is increased, then the chip size is reduced, but the pad area overhead increases proportionally
Solution Approach 1:
The patent segments pads into three distinct types: monitoring pads, package pads, and common pads. Each type serves a specific function and is arranged in separate columns on the memory chip. This segmentation allows for optimized space utilization by preventing functional overlap and enabling independent sizing of each pad type according to its specific requirements, thereby reducing overall pad area overhead.
Solution Approach 2:
The patent applies local quality by assigning different sizes and positions to different pad types based on their specific functional requirements. Monitoring pads are positioned in a first column, package pads in a second column, and common pads in a third column. Each pad type can have locally optimized dimensions and placement, allowing the design to meet specific functional needs while minimizing total pad area occupation on the chip.
2Area of stationary object
If monitoring pads and package pads are arranged separately in columns, then space utilization is optimized, but device complexity increases
Solution Approach 1:
The patent introduces common pads that serve dual functions: they can be used for monitoring during wafer-level testing and for package-level wire connections. This multi-functionality reduces the total number of pads required, as common pads replace the need for separate monitoring and package pads in certain configurations, thereby optimizing space utilization while minimizing the increase in device complexity.
Solution Approach 2:
The patent organizes pads in a columnar arrangement along the periphery of the memory chip, utilizing the two-dimensional surface space efficiently. By arranging monitoring pads, package pads, and common pads in separate columns along the chip edge, the design maximizes the use of available perimeter space without interfering with the core memory array, thus optimizing space utilization while maintaining a systematic and manageable arrangement.
Data Source
AI summary
A method of arranging pads in a semiconductor memory device, the semiconductor memory device using the method, and a processing system having mounted therein the semiconductor memory device. The method includes classifying pads provided in a memory chip of the semiconductor memory device into monitoring pads configured for a memory chip test on a wafer, a package pads configured for wire connection in a package, and common pads configured for both the memory chip test on the wafer and wire connection in the package and arranging the monitoring pads and the package pads separately in columns on the memory chip.