Memory Pad Access Circuit With ESD Protection and Tester Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of system-on-chip (SoC) designs due to shrinking transistor dimensions and oxide layer thicknesses intensifies electrostatic discharge (ESD) protection challenges, leading to higher runtime and memory area consumption, particularly in automotive applications where ESD protection mechanisms are inadequate for secure testing and communication with external sensors and actuators.
Innovation Solution
A memory device with enhanced ESD protection and secure access is implemented, featuring mixed pads that connect to testing machines through both low-speed and high-speed paths, utilizing a three-state multiplexer block, tester presence detector circuit, and logical gate to ensure authorized access and efficient ESD current diversion, along with a method for detecting and verifying bit sequences to grant access to memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection structures are provided for each transistor in SoC, then ESD protection reliability is improved, but device area and runtime consumption increase significantly
Solution Approach 1:
The patent segments the ESD protection approach by providing ESD protection structures only at critical locations (testing pads and selected I/O pads) rather than for every transistor. This selective segmentation maintains ESD protection reliability at vulnerable interfaces while dramatically reducing the overall device area consumption compared to universal transistor-level protection.
Solution Approach 2:
The patent applies local quality by differentiating ESD protection requirements across different pads. Testing pads receive full ESD protection structures, while internal pads receive no protection, and I/O pads receive conditional protection based on their specific vulnerability. This localized approach optimizes the balance between reliability and area efficiency.
2Reliability
If ESD protection structures are provided for each transistor in SoC, then ESD protection reliability is improved, but runtime consumption increases
Solution Approach 1:
The patent segments ESD protection activation to only those pads requiring it during specific operational modes. The testing machine can selectively enable ESD protection structures only when performing tests on external pads, rather than maintaining all protection structures active during normal operation, thereby reducing runtime consumption while preserving reliability when needed.
Solution Approach 2:
The patent implements dynamic ESD protection where the protection structures can be selectively enabled or disabled based on operational mode. During normal device operation, ESD protection is minimized or disabled to reduce runtime overhead. During testing operations, the protection structures are dynamically activated to provide necessary ESD protection, thus optimizing the trade-off between reliability and runtime consumption.
3Adaptability or versatility
If testing pads are provided for external machine contact, then secure testing access is enabled, but ESD exposure risk increases
Solution Approach 1:
The patent converts the harmful ESD exposure risk of testing pads into a beneficial protection mechanism by providing dedicated ESD protection structures specifically at these pads. The testing pads, which inherently expose the device to external ESD threats, are equipped with robust ESD protection networks that safely divert ESD currents, thereby transforming the vulnerable interface into a protected one while maintaining full testing access capability.
Solution Approach 2:
The patent introduces ESD protection structures as intermediary elements between the external testing machine and the internal device circuitry. These protection structures act as mediators that intercept and safely divert ESD currents from external sources before they can reach sensitive internal components, thereby enabling secure testing access while mitigating ESD exposure risk.
4Adaptability or versatility
If mixed pads with both low-speed and high-speed paths are implemented, then communication versatility is improved, but device complexity increases
Solution Approach 1:
The patent implements mixed pads that serve multiple functions - they can operate as testing pads with ESD protection, as I/O pads with or without ESD protection, and support both low-speed and high-speed communication paths. This multi-functionality reduces the total number of dedicated pad types needed, thereby improving communication versatility while actually reducing overall device complexity through consolidation rather than multiplication of structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively addresses ESD protection issues by enabling secure and efficient communication with memory devices, reducing silicon area usage and allowing different test modes while ensuring authorized access, thus enhancing the reliability and security of memory devices in automotive systems.
Implementation Method 1
ESD protection is realized by providing alternative paths for ESD derived currents
Implementation Method 2
three state multiplexer block connected to the memory cells and to the boundary cells and configured to receive thereto a first input signal and a second input signal
Implementation Method 3
tester presence detector circuit configured to provide a presence signal to the logical gate when a testing machine is connected to the mixed pad
Data Source
AI summary
The present disclosure relates to a memory device comprising:an array of memory cells;a plurality of boundary cells able to manage serial and parallel data;mixed pads connected to the memory cells through low speed paths, the mixed pads being configured to be contacted by probes of a testing machine;high speed pads connected to the boundary cells through high speed paths;a three state multiplexer block connected to the memory cells and to the boundary cells and configured to receive thereto at least a first input signal and a second input signal, the three state multiplexer block being also connected to the mixed pads;ESD networks connected to the mixed pads;an enabling circuit connected to one of the mixed pads, configured to receive an external enabling signal and to provide the three state MUX with an internal enabling signal;wherein the enabling circuit comprises:a tester presence detector circuit connected to the mixed pad; anda logical gate having respective input terminals connected to the tester presence detector circuit and configured to receive the external enabling signal, and an output terminal configured to provide the internal enabling signal,the tester presence detector circuit configured to provide a presence signal to the logical gate when a testing machine is connected to the mixed pad.The disclosure also relates to a System-on-Chip (SoC) component comprising a memory device, namely as embedded device as well as to a method implementing an enhanced ESD protection and a secure access to memory cells.