Memory I/O Pad Inductor Layout for High-Speed Signal Integrity
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Solution Overview
Problem
As semiconductor memory devices increase in operating speed, signal integrity (SI) characteristics deteriorate due to increased data rates while maintaining channel characteristics, necessitating measures to improve SI without expanding layout area.
Innovation Solution
Incorporating inductors that vertically overlap input/output pads within the semiconductor memory device's lower wiring layers, specifically in the uppermost layer, to enhance gain at high frequencies and cut-off frequency while minimizing layout area expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data rate is increased to improve operating speed, then productivity is improved, but signal integrity deteriorates
Solution Approach 1:
An inductor is introduced as an intermediary element between the input/output pad and the receiving interface circuit. The inductor has a first terminal connected to the input/output pad and a second terminal connected to the receiving interface circuit, serving as a mediator that improves signal integrity by providing inductance to compensate for signal degradation at high data rates without requiring layout area expansion
Solution Approach 2:
The patent changes the electrical parameters of the circuit by introducing an inductor with specific inductance value. This parameter change allows the circuit to maintain signal integrity at high data rates by adding inductive reactance that compensates for capacitive effects and impedance mismatches in the transmission path
2Reliability
If inductor is added to improve signal integrity, then reliability is improved, but device complexity increases
Solution Approach 1:
The inductor is merged with the existing peripheral structure by disposing it to overlap the input/output pad in the vertical direction. The inductor is integrated into the lower wiring layers (first through fifth lower wiring layers) that are already part of the device structure, combining the inductor function with the existing multi-layer wiring architecture without adding separate discrete components
Solution Approach 2:
The inductor is positioned in the vertical dimension by disposing it to overlap the input/output pad, utilizing the third dimension (vertical stacking) rather than expanding in the horizontal plane. This allows the inductor to be embedded within the existing layout footprint by using unused vertical space above the input/output pad structure
3Area of stationary object
If inductor is disposed to overlap input/output pad, then area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The inductor structure is segmented into multiple parts distributed across different wiring layers (first through fifth lower wiring layers). Each segment is formed in a separate layer, allowing independent formation and reducing the need for high-precision single-step alignment. The segmented structure is connected through vertical vias that pass through dielectric layers, dividing the manufacturing process into manageable stages
Data Source
AI summary
A semiconductor memory device includes a substrate; a peripheral structure including a plurality of lower wiring layers that are vertically stacked on the substrate; a memory structure disposed on the peripheral structure, and including a memory cell array in a first region; an input/output pad disposed over the memory structure in a second region; and an inductor disposed in at least one of the plurality of lower wiring layers and to vertically overlap the input/output pad.