3D Memory Pad Layout for Uniform Transistor Switching Speed

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Solution Overview

Problem

The existing semiconductor memory devices face challenges in maintaining uniform operating speeds across different circuits due to variations in hydrogen diffusion, which affects the characteristics of transistors, particularly those closer to or farther from through contact regions, leading to inconsistent performance.

Innovation Solution

The semiconductor memory device design ensures that the distance between input/output pad electrodes and the closest through contact regions is kept consistent, with a difference of 400 nm or less, to minimize hydrogen influence and maintain uniform operating speeds across all circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If through contact regions are placed close to input/output pad electrodes to reduce wiring length, then connection efficiency improves, but transistor characteristics vary due to hydrogen diffusion

Engineering Contradiction:
Improveconnection efficiencyVSAvoidtransistor characteristic uniformity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a dedicated region between the through contact region and input/output pad electrode where hydrogen diffusion is controlled. This creates a local zone with specific properties (reduced hydrogen concentration) that protects transistor characteristics in that particular area, while allowing other regions to maintain their design optimizations.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces an intermediate region that acts as a buffer zone between the through contact region and input/output pad electrodes. This intermediary structure mediates the hydrogen diffusion process, preventing direct interaction between hydrogen from through contacts and transistors near pad electrodes, thus maintaining characteristic uniformity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If circuits are arranged at different distances from through contact regions, then design flexibility improves, but operating speed uniformity deteriorates

Engineering Contradiction:
Improvedesign flexibilityVSAvoidoperating speed uniformity
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent creates an equipotential environment regarding hydrogen diffusion by establishing controlled regions that ensure all circuits experience similar hydrogen concentrations. This is achieved by defining specific geometric relationships and distance constraints that equalize the diffusion conditions across different circuit locations.

Inventive Principle:
Principle #12Equipotentiality

Solution Approach 2:

The patent controls the distance parameter between circuits and through contact regions, maintaining it within 400 nm or less. By adjusting and constraining this geometric parameter, the patent ensures uniform hydrogen diffusion conditions across all circuits, thereby achieving consistent operating speeds while preserving design flexibility.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces variations in transistor characteristics and operating speeds, ensuring that all circuits connected to the input/output pad electrodes operate at the same speed, thereby enhancing the overall performance and reliability of the memory device.

Implementation Method 1

variations in hydrogen diffusion, which affects the characteristics of transistors

Methodology Applied
Scientific EffectHydrogen diffusion: Diffusion

Data Source

PatentUS11923324B2Semiconductor memory device
Publication Date: 2024.03.05 KIOXIA CORP
  • US11923324B2 patent drawing
  • US11923324B2 patent drawing
  • US11923324B2 patent drawing

AI summary

A semiconductor memory device includes a substrate, a memory cell array separated from the substrate, and a plurality of first bonding pad electrodes away from the memory cell array. The substrate includes a plurality of first and second regions arranged alternately. The memory cell array includes a plurality of conductive layers extending across the plurality of first and second regions, a plurality of semiconductor layers disposed in the plurality of first regions, and a plurality of first contacts disposed in the plurality of second regions. When a distance between a center position of the first bonding pad electrode and a center position of the first contact closest to the first bonding pad electrode is defined as a first distance, a difference between a largest first distance and a smallest first distance among a plurality of first distances is 400 nm or less.