Memory Chip Pad Interconnection Layout for Shared Mask Production
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Solution Overview
Problem
Current semiconductor manufacturing processes require different mask sets for producing semiconductor chips of varying memory capacities, leading to inefficiencies in production, increased costs, and reduced mass production yield.
Innovation Solution
A semiconductor device and manufacturing method where a single mask set is used to produce both single and dual chips by bonding an array chip with a circuit chip, utilizing a shared interconnection layer for electrical connections between pads, allowing for efficient production of chips with different capacities without the need for multiple mask sets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If different mask sets are used for producing semiconductor chips of varying memory capacities, then manufacturing precision can be maintained for each chip type, but device complexity and production costs increase
Solution Approach 1:
The patent implements a universal mask set that can produce both single-chip and dual-chip memory devices through a common manufacturing process. The interconnection layer is designed with a unified structure that accommodates both chip configurations, allowing the same mask to define pads and connections for either single or dual chip arrangements, thereby eliminating the need for multiple specialized mask sets while maintaining manufacturing precision
Solution Approach 2:
The patent segments the manufacturing process into modular stages where the interconnection layer is formed first with a unified pad structure, then subsequently configured for either single or dual chip implementations. This segmentation allows the common interconnection infrastructure to support multiple chip configurations without requiring separate mask sets for each variant
2Adaptability or versatility
If different mask sets are prepared for various chip capacities, then each chip type can be optimized for its specific function, but productivity decreases due to increased process complexity
Solution Approach 1:
The unified mask set is designed to produce memory devices with different capacities through a single manufacturing process. The interconnection layer configuration allows flexible adaptation to single-chip or dual-chip layouts, enabling the same mask to generate various chip capacity configurations without requiring separate production lines or additional masking steps, thereby maintaining high productivity
Solution Approach 2:
The patent employs a dynamic manufacturing approach where the same mask set can produce different chip configurations based on subsequent processing choices. The interconnection layer is formed with inherent flexibility that allows it to be configured for either single or dual chip implementations in later stages, enabling adaptive production of various chip capacities without compromising productivity
3Manufacturing precision
If separate mask sets are used for single and dual chip production, then each mask can be optimized for its specific configuration, but manufacturing cost increases
Solution Approach 1:
The patent develops a universal mask set that eliminates the need for separate mask sets for single and dual chip production. The mask is designed with a unified pad and interconnection pattern that can be used for both chip configurations, reducing mask set costs while maintaining the ability to optimize each configuration through subsequent processing steps rather than requiring dedicated masks
4Manufacturing precision
If multiple mask sets are prepared for different chip types, then manufacturing precision for each type is maintained, but loss of time occurs due to mask set changes
Solution Approach 1:
The unified mask set eliminates the need for mask set changes between single and dual chip production. The same mask can be used continuously to produce both chip types by varying subsequent processing parameters, eliminating mask change downtime while maintaining manufacturing precision through the mask's inherent design that accommodates both configurations
Data Source
AI summary
In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.