Nonvolatile Memory Page Buffer Mapping Data Cache
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing nonvolatile memory systems face delays in responding to host commands due to the time-consuming process of loading mapping data from the memory cell array into the page buffer during read or write operations, which affects performance, especially in portable devices where storage capacity for mapping data may be limited.
Innovation Solution
A nonvolatile memory system that preloads mapping data into a page buffer, allowing for immediate translation of logical addresses to physical addresses when host commands are received, thereby reducing delay times and increasing cache capacity without expanding the system's size by using the page buffer as a cache for mapping data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If mapping data is loaded from the nonvolatile memory cell array into the page buffer during read or write operations, then address translation can be performed, but response time to host commands increases due to the time-consuming loading process
Solution Approach 1:
The patent pre-loads mapping data into the page buffer before host commands are received. The memory controller identifies frequently accessed logical addresses and loads their corresponding mapping data into the page buffer in advance, so that when host commands arrive, the mapping data is already available for immediate address translation, eliminating the time-consuming loading process during command execution
Solution Approach 2:
The patent dynamically manages the page buffer by selectively loading mapping data based on access patterns. The memory controller monitors host command patterns and dynamically adjusts which mapping data is loaded into the page buffer, ensuring that the most frequently accessed mapping data is cached while maintaining flexibility to adapt to changing access patterns
2Quantity of substance
If the page buffer is used to cache mapping data, then cache capacity increases and response time decreases, but the system's physical size would need to expand
Solution Approach 1:
The patent makes the page buffer multi-functional by using it for both its traditional purpose (buffering data during read/write operations) and as a cache for mapping data. This allows the same hardware resource to serve dual purposes, increasing effective cache capacity for mapping data without requiring additional physical memory structures or expanding the system size
3Speed
If mapping data is stored in the nonvolatile memory cell array, then storage capacity is utilized, but access speed is slower compared to cached data
Solution Approach 1:
The patent segments the mapping data storage into two parts: frequently accessed mapping data is loaded into the page buffer for fast access, while less frequently accessed mapping data remains in the nonvolatile memory cell array. This segmentation allows the system to optimize for speed when accessing hot data while maintaining adequate storage capacity utilization for cold data
Data Source
AI summary
A nonvolatile memory system includes: a nonvolatile memory device that includes a nonvolatile memory cell array and a page buffer; and a memory controller that loads into the page buffer mapping data that is stored in the nonvolatile memory cell array, and in response to a logical address received from outside the memory controller, translates the logical address into a physical address based on the mapping data that is loaded into the page buffer.