Nonvolatile Memory Page Buffer Pass/Fail Checking via Address Segmentation
Solution Overview
Problem
Existing nonvolatile memory devices require repeated pass/fail checks across page buffers to determine error correction capability, which is inefficient due to the need to recheck addresses and count fail bits within grouped page buffers.
Innovation Solution
A nonvolatile memory device and method that perform a pass/fail check operation by discharging sense nodes coupled to unselected page buffers using upper bits of the column address, allowing for sequential selection and comparison of current levels across page buffers with identical upper bits, thereby generating pass or fail signals based on error correction code bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If page buffers are grouped by position for pass/fail checking, then the checking can be performed systematically, but address rechecking is required and operational complexity increases
Solution Approach 1:
The patent segments the pass/fail checking process by dividing page buffers into groups based on column address upper bits. Each group corresponds to a specific segment of the address space, allowing the masking circuit to selectively enable only relevant page buffers for checking. This segmentation eliminates the need to recheck addresses across all page buffers, reducing operational complexity while maintaining systematic checking.
Solution Approach 2:
The masking circuit performs preliminary action by pre-configuring which page buffers should be active for the current pass/fail check based on the column address upper bits. This preliminary configuration ensures that only the necessary page buffers are enabled before the checking operation begins, preventing unnecessary operations and reducing the complexity of address management during the checking process.
2Reliability
If all page buffers are checked sequentially, then comprehensive error detection is achieved, but processing time increases
Solution Approach 1:
The patent divides the comprehensive checking task into segments based on column address upper bits. Instead of checking all page buffers in a single sequential pass, the masking circuit enables only the relevant segment of page buffers corresponding to the current address range being checked. This segmentation maintains error detection completeness for each segment while significantly reducing the time required compared to checking all page buffers sequentially.
Solution Approach 2:
The patent applies partial action by enabling only the necessary subset of page buffers for each pass/fail check operation rather than all page buffers. The masking circuit determines which page buffers are relevant based on column address upper bits and enables only those, performing partial checking that is sufficient for the current operation while reducing overall processing time.
3Speed
If page buffers are selected without address-based masking, then operation speed increases, but address verification accuracy decreases
Solution Approach 1:
The masking circuit acts as an intermediary between the column address input and the page buffer selection process. It takes the column address upper bits as input and generates control signals that selectively enable the corresponding page buffers. This intermediary ensures that address verification accuracy is maintained by correctly mapping addresses to page buffers, while still allowing fast operation since the masking logic operates in parallel with the checking process.
Solution Approach 2:
The masking circuit performs preliminary action by pre-determining which page buffers should be enabled based on the column address upper bits before the actual pass/fail checking begins. This preliminary address-based selection ensures verification accuracy is maintained while allowing the subsequent checking operation to proceed at high speed without address rechecking delays.
Data Source
AI summary
A nonvolatile memory device includes a page buffer unit configured to include a plurality of page buffers coupled to the respective bit lines; a pass/fail circuit coupled to the page buffer unit and configured to perform a pass/fail check operation by comparing the amount of current, varying according to verify data stored in the plurality of page buffers, with an amount of reference current corresponding to the number of allowed error correction code bits; and a masking circuit configured to preclude the pass/fail check operation by coupling a ground terminal to sense nodes coupled to the remaining page buffers, respectively, other than page buffers corresponding to column addresses having the identical upper bits as an input column address.