Semiconductor Memory Page Buffer Coupling Circuit for Local I/O Line Speed
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Solution Overview
Problem
The existing semiconductor memory devices face challenges in improving operating speed due to the time required for outputting data from the output terminal and inverse output terminal of the page buffer to the global word line, which is affected by the length of local I/O lines and parasitic capacitance, leading to increased power consumption and reduced voltage difference detection efficiency.
Innovation Solution
The semiconductor memory device incorporates a first and second page buffer group coupled to memory arrays through bit lines, with a coupling circuit that connects the output and inverse output terminals of selected page buffers to local I/O lines, and a sense amplifier that detects voltage differences between these lines to output data to a global I/O line, while reducing the length of local lines to half to enhance precharge speed and voltage difference detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the length of local I/O lines is reduced, then the operating speed is improved and power consumption is reduced, but the device complexity increases due to the need for coupling circuits and multiple page buffer groups
Solution Approach 1:
The memory device is divided into multiple memory arrays (first and second memory arrays) with corresponding page buffer groups (first and second page buffer groups). Each page buffer group has its own local I/O lines, which are shorter than a single unified local I/O line would be. This segmentation reduces the length of local I/O lines, thereby improving operating speed and reducing power consumption while managing device complexity through modular organization.
Solution Approach 2:
A coupling circuit is introduced as an intermediary component to connect the output terminals and inverse output terminals of selected page buffers to the local I/O lines. This coupling circuit enables efficient data transfer between the page buffers and local I/O lines, achieving fast operating speed without requiring a complex reorganization of the entire memory structure.
2Loss of energy
If the length of local I/O lines is reduced, then power consumption is reduced, but the device complexity increases due to additional coupling circuits
Solution Approach 1:
The memory system is segmented into multiple independent memory arrays and page buffer groups, each with dedicated local I/O lines. This segmentation reduces the total length of local I/O lines, which directly reduces power consumption during data transfer operations. The modular structure manages complexity by creating repeatable units that can be systematically organized.
Solution Approach 2:
The physical parameter of local I/O line length is changed by introducing multiple shorter local I/O lines instead of fewer longer ones. This parameter change reduces the capacitance and resistance of the signal paths, thereby reducing power consumption. The coupling circuits are designed to work efficiently with these shorter lines, optimizing the overall power-performance tradeoff.
3Loss of time
If the length of local I/O lines is reduced, then the time for outputting data is reduced, but the device complexity increases due to the coupling circuit configuration
Solution Approach 1:
The memory device is segmented into multiple memory arrays with corresponding page buffer groups, where each group has dedicated local I/O lines. This segmentation reduces the length of local I/O lines, which directly reduces the time required for data output operations. The modular architecture manages complexity by creating systematic, repeatable units that simplify design and fabrication.
Solution Approach 2:
The coupling circuit is configured to selectively connect specific page buffer output terminals to the local I/O lines based on column select signals. This preliminary configuration of connections allows data to be quickly routed to the appropriate local I/O lines without requiring complex dynamic switching during the data output process, thereby reducing data output time while managing complexity through pre-established connection paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the time for data output to the global word line, improves operating speed, and decreases power consumption by lowering precharge voltage and parasitic capacitance, allowing for faster voltage difference detection and increased efficiency in data transfer.
Implementation Method 1
a sense amplifier configured to detect a voltage difference between the first local I/O line and the first inverse local I/O line or a voltage difference between the second local I/O line and the second inverse local I/O line
Data Source
AI summary
A semiconductor memory device includes a first page buffer group including a plurality of page buffers coupled to memory cells of a first memory array through bit lines, a second page buffer group, a coupling circuit configured to couple an output terminal and an inverse output terminal of a selected page buffer of the first page buffer group to a first local I/O line and a first inverse local I/O line, respectively, or an output terminal and an inverse output terminal of a selected page buffer of the second page buffer group to a second local I/O line and a second inverse local I/O line, respectively, in response to a column select signal, and a sense amplifier configured to detect a voltage difference between the first local I/O line and the first inverse local I/O line or between the second local I/O line and the second inverse local I/O line.