3D Memory Page Buffer Inter-Die Coupling
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Solution Overview
Problem
In 3D memory arrays, relaxed design rules to achieve high memory density result in reduced data rates due to fewer bit lines coupling selected memory cells to the page buffer, leading to a trade-off between memory cell area and data rate, necessitating a solution that enhances data rate without reducing available area for a given die size.
Innovation Solution
A memory device structure with a 3D array level die comprising multiple sub-arrays and a page-buffer level die, where inter-die connections electrically couple page buffers to data lines of corresponding sub-arrays, allowing for improved data rate and maintaining the available area for memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If 3D memory arrays use relaxed design rules to achieve high memory density, then memory cell area is improved, but data rate deteriorates due to fewer bit lines coupling selected memory cells to the page buffer
Solution Approach 1:
The patent divides the 3D memory array into multiple sub-arrays, each with its own dedicated page buffer. This segmentation allows parallel access to multiple sub-arrays simultaneously, increasing the overall data rate while maintaining relaxed design rules for individual sub-arrays. The bit lines are also segmented to correspond with sub-arrays, enabling independent operation of each sub-array-page buffer pair.
Solution Approach 2:
The patent transitions from a two-dimensional array structure to a three-dimensional stacked architecture with multiple levels of memory cells. This dimensional change increases storage density without increasing the footprint area, while the vertical stacking allows for more bit lines to be coupled to page buffers in the third dimension, thereby improving data rate despite relaxed lateral design rules.
2Productivity
If 3D memory arrays divide into sub-arrays with dedicated page buffers to improve data rate, then data rate is improved, but device complexity worsens due to larger area required for page buffers
Solution Approach 1:
The patent stacks the page buffer level die above the array level die in the vertical dimension, utilizing the third dimension to house page buffers without increasing the lateral footprint area. This 3D stacking architecture allows multiple page buffers to be integrated in parallel, supporting high data rates while maintaining a compact form factor.
Solution Approach 2:
The patent introduces inter-die connection structures (such as through-silicon vias or bump bonds) as intermediaries to electrically couple the page buffers on the upper die to the bit lines on the lower array die. These inter-die connections enable signal transmission between levels without requiring lateral expansion, thus reducing the overall device footprint while maintaining functionality.
3Productivity
If inter-die connections are used to couple page buffers to sub-arrays, then data rate is improved through parallel operations, but manufacturing precision requirements worsen
Solution Approach 1:
The patent incorporates alignment marks and registration features during the fabrication process to pre-establish precise positional relationships between inter-die connection structures on different dies. These preliminary alignment features are formed during manufacturing to guide subsequent bonding or stacking operations, ensuring accurate alignment without requiring post-fabrication adjustment.
Solution Approach 2:
The patent designs self-aligned inter-die connection structures where the connection features on one die automatically register with corresponding features on the other die through mechanical interlocking or magnetic alignment during the stacking process. This self-alignment mechanism reduces dependency on external alignment equipment and minimizes precision requirements during assembly.
Data Source
AI summary
A structure of a memory device and a method for making the memory device structure are described. The memory device includes an array of memory cells in an array level die. The array comprises a plurality of sub-arrays. Each of the sub-arrays comprises respective data lines. The memory device also includes page buffers for corresponding sub-arrays in a page-buffer level die. The memory device also includes inter-die connections that are configured to electrically couple the page buffers in the page-buffer level die to data lines of corresponding sub-arrays in the array level die.