Memory Device Pass Transistors Sub-Block Segmentation
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Solution Overview
Problem
Conventional memory devices face performance hindrances due to an increase in the number of sub-blocks, leading to higher energy consumption and longer operation times, particularly in memory operations such as read and write operations.
Innovation Solution
The memory device is structured with a lower number of sub-blocks and a higher number of blocks for a given area, utilizing multiple pass transistors to selectively control access lines and data lines, allowing for efficient signal management and reduced energy consumption through the use of unique signal combinations and voltage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of sub-blocks is increased to achieve higher storage density, then storage density is improved, but performance deteriorates due to higher energy consumption and longer operation times
Solution Approach 1:
The memory device is divided into multiple blocks, with each block containing multiple sub-blocks. This hierarchical segmentation allows selective access to specific sub-blocks within active blocks, reducing the effective number of sub-blocks that need to be managed at any given time and improving overall performance while maintaining high storage density.
Solution Approach 2:
The patent implements dynamic block and sub-block selection mechanisms where not all blocks or sub-blocks are active simultaneously. By dynamically activating only the necessary blocks and sub-blocks for current operations, the system reduces energy consumption and operation time while maintaining the capability for high storage density when all blocks are utilized.
2Quantity of substance
If the number of sub-blocks is increased for a given device area, then storage density is improved, but energy consumption increases
Solution Approach 1:
The system dynamically activates only the blocks and sub-blocks that are currently needed for read or write operations. This dynamic activation reduces the number of simultaneously active components, thereby lowering energy consumption while maintaining the physical capacity for high storage density through the organized block and sub-block structure.
Solution Approach 2:
By segmenting the memory into blocks and sub-blocks with selective access capabilities, the system can isolate active regions from inactive regions. This segmentation allows power management to disable or reduce power to inactive sub-blocks, reducing overall energy consumption while preserving the high storage density architecture.
3Quantity of substance
If the number of sub-blocks is increased for a given device area, then storage density is improved, but operation time increases
Solution Approach 1:
The hierarchical block and sub-block structure enables selective access to specific sub-blocks within active blocks. This segmentation reduces the search and access time by limiting the scope of operations to only the necessary sub-blocks rather than scanning through all sub-blocks, thereby reducing operation time while maintaining high storage density.
Solution Approach 2:
The dynamic selection and activation of blocks and sub-blocks allows the system to quickly identify and access only the relevant memory regions for current operations. This dynamic addressing reduces operation time by avoiding unnecessary access to inactive blocks and sub-blocks, while the overall high storage density is maintained through the complete block-subblock hierarchy.
Data Source
AI summary
Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. The transistors include sources and drains formed from portions of the semiconductor material. The transistors include gates that are electrically uncoupled to each other.