Nonvolatile Memory Peak Current Decentralization
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Solution Overview
Problem
Conventional nonvolatile memory systems face instability and reliability issues due to peak current surges when multiple flash memory chips operate simultaneously, leading to potential power supply instability, which is typically addressed through hardware design modifications that lack flexibility.
Innovation Solution
A software-based approach where a controller chip sends commands to nonvolatile memory chips at different time points, decentralizing their operation to reduce peak current, without requiring changes to the hardware architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple flash memory chips are operated simultaneously to increase memory capacity, then the memory capacity is improved, but the peak current increases proportionally causing power supply instability
Solution Approach 1:
The patent segments the simultaneous operation of multiple flash memory chips into sequential operations by dividing the chip set into groups and issuing commands to different groups at different time points. This segmentation of the operation timeline reduces the peak current while maintaining the total memory capacity access capability.
Solution Approach 2:
The patent dynamically adjusts the operation timing of different flash memory chips based on their group assignments. By making the operation schedule dynamic and adaptive rather than simultaneous, the system reduces peak current demands while still providing high-speed access through parallel processing of multiple groups.
2Reliability
If hardware design is modified to decentralize peak current, then the power supply stability is improved, but the device complexity increases
Solution Approach 1:
The patent replaces hardware-based current management mechanisms (such as physical delay circuits or separate power supply paths) with a software-based command scheduling approach. The controller chip uses firmware to manage the timing of commands issued to different flash memory groups, eliminating the need for additional hardware components while achieving the same current decentralization effect.
3Reliability
If flash memory chips are erased sequentially to reduce peak current, then the power supply stability is improved, but the operation speed decreases
Solution Approach 1:
The patent segments the flash memory chips into multiple groups that can be operated in parallel within each time slot. While groups are processed sequentially to reduce peak current, each group itself can operate in parallel, maintaining high-speed performance within the constraints of reduced peak current demands.
Solution Approach 2:
The patent implements periodic action by cycling through different groups of flash memory chips in a structured sequence. Each group receives commands in time slots dedicated to that group, creating a periodic pattern of operation that smooths out peak current while maintaining overall high throughput through the systematic rotation between groups.
Data Source
AI summary
A nonvolatile memory system has a controller chip connected to a memory medium and several nonvolatile memory chips. The memory medium stores program codes for the controller chip to distribute an operation of the nonvolatile memory chips upon an instruction over time, so as to decentralize the peak current caused by the operation and thereby improve the stability of the system.