Semiconductor Memory Peripheral Wiring Via Penetration

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Solution Overview

Problem

Current semiconductor memory devices face challenges in efficiently integrating peripheral upper wirings with lower wirings and dielectric layers, leading to issues with electrical connectivity and signal delay due to variations in wiring thickness and dielectric layer thickness across different regions.

Innovation Solution

A semiconductor memory device design featuring a semiconductor substrate with a cell region and peripheral region, where a mold layer with an etching stopper layer is used to facilitate the penetration of peripheral upper wirings through the dielectric layers, ensuring electrical connectivity and reducing signal delay by maintaining consistent wiring thickness and dielectric layer thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If peripheral upper wiring penetrates through mold layer and upper dielectric layer to connect with peripheral lower wiring, then electrical connectivity is improved, but manufacturing complexity increases due to multiple layer penetration requirements

Engineering Contradiction:

Improveelectrical connectivityVSAvoidmanufacturing complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the wiring structure into multiple segments: peripheral lower wiring in the lower dielectric layer, peripheral upper wiring penetrating through the mold layer and upper dielectric layer, and intermediate via portions. This segmentation allows each component to be optimized independently while maintaining overall connectivity, resolving the contradiction between reliability and manufacturing complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The peripheral upper wiring extends in the vertical dimension by penetrating through multiple dielectric layers via via portions, rather than only in the horizontal plane. This dimensional transition enables direct electrical connection between lower and upper wirings, improving connectivity while providing a systematic approach to managing multi-layer complexity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Loss of time

If wiring thickness and dielectric layer thickness are maintained consistently across regions, then signal delay is reduced, but adaptability to different device configurations decreases

Engineering Contradiction:

Improvesignal delayVSAvoiddesign adaptability

Core Design Contradiction:

Loss of timeVSAdaptability or versatility

Solution Approach 1:

The patent applies different thickness characteristics to different regions: the wiring portion has greater thickness for low signal delay, while the via portions have reduced thickness to accommodate penetration through dielectric layers. This local differentiation allows the structure to optimize signal performance in critical areas while maintaining adaptability in other regions.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent varies the thickness parameter of the peripheral upper wiring across different portions: the wiring portion has a first thickness greater than the bit line thickness, while the via portions have a second thickness that is smaller. This parameter variation enables simultaneous optimization of signal delay and design adaptability for different device configurations.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If peripheral upper wiring includes multiple via portions extending downward, then connectivity to lower wiring is ensured, but manufacturing precision requirements increase

Engineering Contradiction:

Improveelectrical connectivityVSAvoidvia portion alignment

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent introduces the etching stopper layer as an intermediary between the upper dielectric layer and the lower dielectric layer. This stopper layer serves as a reference plane for forming via portions, enabling precise alignment and positioning of multiple via portions without requiring extremely high manufacturing precision throughout the entire structure.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The etching stopper layer is formed in advance before the via portions are created. This preliminary action establishes a predetermined reference structure that guides the subsequent formation of via portions, ensuring their proper alignment and positioning while simplifying the manufacturing process and reducing precision requirements.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10504959B2Semiconductor memory device

Publication Date: 2019.12.10 SAMSUNG ELECTRONICS CO LTD

AI summary

A lower dielectric layer is disposed on a semiconductor substrate. A plurality of peripheral lower wirings are disposed on a peripheral region of the semiconductor substrate and in the lower dielectric layer. An upper dielectric layer is disposed on the lower dielectric layer and covers the plurality of peripheral lower wirings. A mold layer is disposed on the upper dielectric layer and includes an etching stopper layer. A peripheral upper wiring penetrates the mold layer and the upper dielectric layer to be connected to at least one of the plurality of peripheral lower wirings. The peripheral upper wiring includes a wiring portion, a first via portion extending downwardly from a bottom surface of the wiring portion, and a second via portion extending downwardly from the bottom surface of the wiring portion.