Memory Device Phase Synchronization Training Circuit
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Solution Overview
Problem
Memory devices face challenges in synchronizing data and strobe signals due to variable latencies, making it difficult for data latching circuits to latch signals at the right timing.
Innovation Solution
A memory device with a training circuit, data strobe transmission path, data transmission paths, data latching circuits, and phase detection circuits, where the training circuit generates clock signals to adjust the delay time of adjustable delay circuits until the clock signals are in phase, ensuring synchronized data and strobe signal arrival at the latching circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data signal and data strobe signal are transmitted through separate paths, then data transmission capability is improved, but variable latencies cause timing synchronization problems
Solution Approach 1:
The patent applies preliminary action by introducing a training mode that operates before normal data transmission. During training mode, the training circuit generates training clock signals to adjust the delay circuits in advance, so that the data and strobe signals are pre-synchronized. This preliminary adjustment ensures that when normal operation resumes, the signals arrive at the latching circuit simultaneously without requiring continuous real-time adjustment during data transmission.
2Measurement precision
If delay circuits are added to synchronize signals, then timing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies dynamics by making the delay circuits adjustable rather than fixed. The delay circuits can be dynamically configured during training mode to compensate for varying path latencies, and then locked into their optimized states for normal operation. This dynamic adjustability allows the system to adapt to different timing conditions without requiring overly complex fixed compensation circuits for every possible scenario.
3Manufacturing precision
If training mode is implemented to synchronize signals, then data latching accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by implementing training mode as an intermittent operation that occurs periodically rather than continuously. The training circuit activates during specific training intervals to adjust and synchronize the timing, then deactivates during normal data transmission operations. This periodic activation allows the system to maintain synchronization accuracy while minimizing power consumption by keeping the training circuit inactive during steady-state operation.
Data Source
AI summary
A memory device including a training circuit, a data strobe transmission path, data transmission paths, data latching circuits and a phase detection circuit is provided. When the memory device is under a training mode, a training process is performed on at least one of the data transmission paths. The phase detection circuit detects a phase difference between signals between the data transmission path and the data strobe transmission path to adjust a delay time of the adjustable delay circuit of the data transmission path until the signals are in phase. When the memory device is under an operation mode, each of the data latching circuits receives a treed data strobe signal from the data strobe transmission path to latch a delayed data signal received from the adjustable delay circuit of one of the data transmission paths.