Memory Cell Pillar Layout to Prevent Bridging From Dielectric Seams
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Solution Overview
Problem
As semiconductor devices undergo continual reductions in minimum feature size, the formation of dielectric pillars with high aspect ratios often results in seams, leading to a risk of bridging during the formation of conductive pillars in memory cells, which can affect the integrity and controllability of memory cell behavior.
Innovation Solution
A pull-back process is implemented to address the seams issue in dielectric pillars, ensuring controllable cell behavior by forming gap filling pillars between conductive pillars, which prevents bridging and maintains the structural integrity of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dielectric pillars with high aspect ratios are formed to increase integration density, then manufacturing precision is improved, but seams form in the dielectric pillars leading to bridging risks
Solution Approach 1:
A gap filling pillar is introduced as an intermediary structure between the first and second conductive pillars. This gap filling pillar, positioned within the seam region of the dielectric pillar, acts as a physical barrier that prevents conductive material from bridging across the seam during subsequent filling operations, thereby eliminating the reliability issue while maintaining the high aspect ratio dielectric pillar structure
Solution Approach 2:
The gap filling pillar is formed in advance before the conductive pillars are created. By pre-positioning this protective structure in the seam area, the patent prevents potential bridging issues before they can occur during the conductive material deposition process, ensuring reliable isolation between conductive elements
2Productivity
If minimum feature size is reduced to increase integration density, then productivity is improved, but seams form in dielectric pillars affecting memory cell integrity
Solution Approach 1:
The patent accepts the inevitable formation of seams in high aspect ratio dielectric pillars as a consequence of high integration density, but converts this harmful feature into a beneficial one by intentionally positioning a gap filling pillar within the seam region. The seam, rather than being a defect to be eliminated, becomes a designated location for placing the protective gap filling structure that prevents bridging
3Reliability
If gap filling pillars are formed between conductive pillars to prevent bridging, then reliability is improved, but device complexity increases
Solution Approach 1:
The gap filling pillar is not introduced as a universal structure throughout the device, but only in the specific local region where seams occur in the dielectric pillars. This localized approach provides bridging prevention exactly where needed, without adding unnecessary complexity to other regions of the memory device structure
Data Source
AI summary
A memory device includes a plurality of first conductive pillars, a plurality of second conductive pillars, a plurality of gap filling pillars, a channel layer and first dielectric pillars. The gap filling pillars are located in between the first conductive pillars and the second conductive pillars. The channel layer is extending in a first direction, and located on side surfaces of the first conductive pillars and the second conductive pillars. The first dielectric pillars are located in between the channel layer and the plurality of gap filling pillars, wherein a length of an interface where the first dielectric pillars contact the gap filling pillars along the first direction is different from a length of the gap filling pillars along the first direction.