Semiconductor Memory Pillars Epitaxial Growth Thermal Management
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Solution Overview
Problem
Current semiconductor storage devices face challenges in efficiently forming transistors above semiconductors on a substrate while minimizing thermal exposure to peripheral circuitry elements and optimizing the angle of side surfaces within the interlayer insulator, which affects the dry etching process and contact formation.
Innovation Solution
The semiconductor storage device is manufactured by forming semiconductors through crystal growth or epitaxial growth within the interlayer insulator, allowing for reduced contact length and perpendicular side surfaces, and sequencing the formation of the memory cell array and peripheral circuitry to avoid thermal exposure and enhance etching precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are formed above semiconductors on the substrate, then memory cell functionality is achieved, but thermal exposure to peripheral circuitry elements increases causing performance degradation
Solution Approach 1:
The substrate surface is divided into a memory cell region and a peripheral circuitry region. Semiconductors are selectively formed only in the memory cell region, while the peripheral circuitry region remains free of semiconductors. This spatial segmentation prevents thermal exposure of peripheral circuitry elements during semiconductor formation processes, maintaining their performance while enabling memory cell functionality.
2Length of moving object
If semiconductors are formed within the interlayer insulator, then contact length is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The interlayer insulator is formed first, creating a pre-defined structure with controlled thickness and position. Semiconductors are then formed within this pre-established interlayer insulator framework. This preliminary formation of the interlayer insulator provides a stable reference structure that guides subsequent semiconductor formation, reducing the actual precision requirements during semiconductor deposition while achieving short contact lengths.
3Manufacturing precision
If side surfaces within the interlayer insulator are optimized for perpendicularity, then dry etching precision is improved, but device complexity increases
Solution Approach 1:
The side surfaces of the interlayer insulator are engineered to have enhanced perpendicularity specifically in the regions where dry etching will occur. This localized optimization of surface quality provides precise etching references without requiring the entire device structure to be more complex. The perpendicular side surfaces are formed only where needed for etching operations, maintaining simplicity elsewhere in the device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of contact failure and maintains the performance of peripheral circuitry elements by minimizing thermal exposure and optimizing the structure for effective dry etching and region utilization.
Implementation Method 1
forming semiconductors through crystal growth or epitaxial growth within the interlayer insulator
Implementation Method 2
forming semiconductors through crystal growth or epitaxial growth within the interlayer insulator
Data Source
AI summary
According to an embodiment, a semiconductor memory device includes a semiconductor substrate. The semiconductor substrate includes a first surface. A first semiconductor layer is provided on a first region of the first surface. A first transistor is provided on the first semiconductor layer. A second semiconductor layer is provided on a second region of the first surface. A second transistor is provided on the second semiconductor layer. A stacked body is provided on a third region of the first surface. The stacked body includes a plurality of conductors and a plurality of memory pillars. A first insulator is provided between the first semiconductor layer and the second semiconductor layer.