Semiconductor Memory Pillar Grain Size Gradient
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Solution Overview
Problem
In three-dimensional nonvolatile semiconductor memory devices, there are challenges with achieving a steep threshold voltage distribution and large cell current, as well as issues with dopant diffusion affecting select gate characteristics, leading to operation failures and sensing difficulties.
Innovation Solution
The semiconductor memory device features channel layers with a larger crystal grain size than cap layers, where the channel layer extends into the stacked body from the uppermost select gate line, and the cap layer is connected to the bit line via a plug, reducing contact resistance and suppressing electron scattering, thereby improving memory cell characteristics and cell current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel layer has a small crystal grain size, then the contact resistance is reduced, but the electron scattering increases and cell current decreases
Solution Approach 1:
The patent applies local quality by creating two distinct regions within the pillar structure: a cap layer with small crystal grain size at the upper portion (in contact with bit line) to reduce contact resistance, and a channel layer with large crystal grain size in the lower portion (extending into stacked body) to reduce electron scattering and increase cell current. This spatial differentiation of material properties resolves the contradiction between low contact resistance and high cell current.
2Ease of manufacture
If dopant diffusion is increased to improve manufacturing, then the select gate characteristics deteriorate leading to operation failures
Solution Approach 1:
The patent uses local quality by forming a cap layer with specific material composition and crystal grain characteristics that acts as a diffusion barrier. This cap layer is positioned locally at the upper portion of the pillar, protecting the select gate region from dopant diffusion while allowing controlled dopant distribution in the channel region, thus maintaining select gate characteristics despite manufacturing dopant diffusion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a steep threshold voltage distribution, enhanced write and read characteristics, and increased memory capacity by reducing dopant diffusion and electron scattering, ensuring reliable operation and improved cell current sensing.
Implementation Method 1
suppressing electron scattering
Implementation Method 2
reducing contact resistance
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked; and a pillar including a channel layer extending in a stacking direction of the plurality of conductive layers in the stacked body, a memory layer provided on a side surface of the channel layer, and a cap layer provided on the channel layer, the cap layer being connected to an upper layer wiring of the stacked body, wherein the channel layer extends into the stacked body at least from a height position of an uppermost conductive layer of the plurality of conductive layers, and a grain size of crystal contained in the channel layer is larger than a grain size of crystal contained in the cap layer.