Semiconductor Memory Pillar Joint Design for Z-Axis Connection
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Solution Overview
Problem
Current semiconductor memory devices face challenges in connecting semiconductor layers within memory pillars effectively, leading to potential division along the Z-axis and affecting current paths, which impacts storage capacity and efficiency.
Innovation Solution
The semiconductor memory device employs a joint portion with specific tapered and constricted shapes in the memory pillar, where the semiconductor layer is connected through boundaries that maintain uniform etching rates, preventing division and enhancing contact with conductor layers, thereby improving current paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory hole is formed in two parts (lower and upper portions) for three-dimensional memory structure, then high integration and large storage capacity are achieved, but the semiconductor layer connection becomes problematic leading to potential division along the Z-axis
Solution Approach 1:
The memory hole formation process is segmented into two parts: a lower portion formed first, then an upper portion formed subsequently. This segmentation allows for better control of the etching process and ensures proper connection of semiconductor layers between the stacked body portions, preventing division along the Z-axis while maintaining high storage capacity.
2Ease of manufacture
If conventional memory hole formation is used, then manufacturing process is simpler, but etching rates are non-uniform causing poor connection at boundaries
Solution Approach 1:
A lower memory hole is formed preliminarily before forming the upper memory hole. This preliminary action establishes a foundation that ensures uniform etching rates when the upper portion is formed subsequently, improving connection quality at boundaries without significantly complicating the overall manufacturing process.
3Ease of manufacture
If the semiconductor layer is connected through boundaries with non-uniform etching, then manufacturing is easier, but parasitic resistance increases affecting read current
Solution Approach 1:
The etching process is designed to maintain continuity and uniformity when forming boundaries between lower and upper stacked body portions. This continuous uniform etching action ensures excellent connection of the semiconductor layer at boundaries, reducing parasitic resistance and improving read current flow through the memory pillar.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a stacked body of first conductor layers and second conductor layers. A pillar including a semiconductor layer extends along through the stacked body in a first direction. A charge storage layer is between the conductor layers and the semiconductor layer. The semiconductor layer includes a first portion extending along the first direction from an uppermost first conductor layer to a lowermost second conductor layer and a second portion above the first portion in the first direction. The second portion has a diameter that decreases with increasing distance along the first direction from the first portion.