3D Memory Pillar Joint Electron Distribution Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor memory devices with three-dimensionally stacked memory cells, the joint portion between memory pillars can lead to uneven electron distribution, causing write errors and widened threshold voltage distributions, which affect data reliability.

Innovation Solution

The semiconductor memory device employs a write operation method where different voltages are applied during the pre-charge operation based on the selected word line, ensuring that electrons are effectively drawn out from the joint portion, using a combination of first and second dummy word lines to manage electron distribution across the memory pillars.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If three-dimensionally stacked memory cells are used to increase storage capacity, then memory density is improved, but uneven electron distribution occurs at the joint portion causing write errors

Engineering Contradiction:
Improvememory storage capacityVSAvoiddata reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

A dummy word line is introduced as an intermediary element between the joint portion and the functional word lines. This dummy word line acts as a mediator to control and equalize electron distribution in the joint portion during write operations, preventing write errors while maintaining high memory density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Different voltage levels are applied to different regions: a first voltage level is applied to the dummy word line adjacent to the joint portion, while a second voltage level is applied to other word lines. This local differentiation of electrical conditions optimizes electron distribution specifically at the problematic joint portion without affecting other memory regions.

Inventive Principle:
Principle #3Local quality

2Reliability

If different voltages are applied to word lines during pre-charge operation, then electron distribution is equalized, but device complexity increases

Engineering Contradiction:
Improveelectron distribution uniformityVSAvoidvoltage control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The word line structure is segmented into functional word lines and a dummy word line, with the dummy word line specifically positioned adjacent to the joint portion. This segmentation allows targeted voltage application only where needed, simplifying the overall control scheme compared to applying different voltages to all word lines.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dummy word line performs a preliminary action by equalizing electron distribution in the joint portion before the actual write operation begins. This pre-conditioning of the joint portion ensures reliable write operations without requiring complex real-time adjustments during the write process.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces write errors and maintains data reliability by inhibiting the number of error bits in read operations and stabilizing the threshold voltage distribution across memory cell transistors.

Implementation Method 1

In the pre-charge operation in a write operation in which the first word line is selected, the controller applies a first voltage higher than a ground voltage to the first word line, the first dummy word line, the second dummy word line, and the second word line

Methodology Applied
Scientific EffectElectron transport: Conduction (electrical)

Data Source

PatentUS10431311B2Semiconductor memory device
Publication Date: 2019.10.01 KIOXIA CORP
  • US10431311B2 patent drawing
  • US10431311B2 patent drawing
  • US10431311B2 patent drawing

AI summary

According to one embodiment, a semiconductor memory includes includes conductors, a pillar through the conductors, a controller. The pillar includes a first pillar portion, a second pillar portion, and a joint portion between the first pillar portion and the second pillar portion. Each of the portions where the pillar and the conductors cross functions as a transistor. Among the conductors through the first pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a first dummy word line and a first word line. Among the conductors through the second pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a second dummy word line and a second word line.