Semiconductor Memory Pillar Joint Structure for Reliable Data Storage
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Solution Overview
Problem
Semiconductor memory devices face deterioration in electrical characteristics at the joint portion of vertically stacked memory pillars, leading to reduced reliability and performance due to misalignment defects and uneven electric field distribution.
Innovation Solution
The semiconductor memory device incorporates a unique structure where the joint portion between vertically stacked pillars lacks block and tunnel insulating films, allowing the semiconductor layer to protrude and receive a stronger electric field, enhancing voltage application and channel formation, and removing sacrificial members to prevent material changes and defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If block and tunnel insulating films are formed at the joint portion of vertically stacked memory pillars, then manufacturing precision is improved, but electrical characteristics deteriorate due to misalignment defects and uneven electric field distribution
Solution Approach 1:
The patent removes block and tunnel insulating films from the joint portion between vertically stacked memory pillars. This extraction eliminates the source of misalignment defects and uneven electric field distribution that occur at the joint portion, thereby improving electrical characteristics without compromising manufacturing precision elsewhere in the device
Solution Approach 2:
The patent applies different structural configurations to different regions: the joint portion lacks block and tunnel insulating films to ensure uniform electric field distribution, while other portions of the memory pillars maintain their standard structure. This local differentiation resolves the contradiction by optimizing each region for its specific function
2Power
If the semiconductor layer protrudes at the joint portion to receive stronger electric field, then voltage application is enhanced, but channel current decreases due to material changes and defects
Solution Approach 1:
The patent converts the previously harmful protrusion structure into a beneficial feature by removing the block and tunnel insulating films. The semiconductor layer now protrudes to receive stronger electric fields for improved voltage application, while the absence of insulating films prevents the material changes and defects that would otherwise cause channel current decrease
3Reliability
If sacrificial members are removed to prevent material changes, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates sacrificial members during the initial formation of block and tunnel insulating films, which are then removed in a subsequent step. This preliminary incorporation allows for complete removal of the sacrificial members, preventing any material changes or defects at the joint portion and ensuring high data reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration prevents channel current decrease and improves performance by ensuring consistent electrical characteristics across the memory pillar, enhancing data reliability and density.
Implementation Method 1
allowing the semiconductor layer to protrude and receive a stronger electric field, enhancing voltage application and channel formation
Data Source
AI summary
A device includes conductor layers and a first pillar, extending through the conductor layers, that includes a first columnar portion, a second columnar portion, and a middle portion between the first and second columnar portions. A diameter of the middle portion is larger than a diameter of the first columnar portion and larger than a diameter of the second columnar portion. The first columnar portion includes a first semiconductor layer and a first charge storage layer. The second columnar portion includes a second semiconductor layer and a second charge storage layer. The middle portion includes a third semiconductor layer. The first and second semiconductor layers are in contact with the third semiconductor layer on a first side and a second side of the third semiconductor layer, respectively. The first charge storage layer is spaced from the second charge storage layer.


