Semiconductor Memory Pillar Structures with Offset Rows
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Solution Overview
Problem
Highly integrated semiconductor memory devices with vertical pillar transistors face issues of increased wiring resistance and electrical shorts due to narrower wiring and closer spacing, leading to poor response speed and electrical characteristics.
Innovation Solution
A semiconductor memory device design featuring alternately disposed rows and columns of active pillar structures with buried bit lines connecting adjacent columns, and offset gate patterns to enhance integration density and reduce wiring resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration is increased by using vertical pillar transistors, then the transistor density is improved, but the wiring resistance increases and electrical shorts occur more frequently
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional wiring structures that extend vertically along the pillar structures. Bit lines and word lines are formed at different heights and depths, creating a multi-layered wiring architecture that reduces crowding and resistance while maintaining high transistor density.
Solution Approach 2:
The wiring structures are nested around and along the vertical pillar transistor structures. Bit lines are formed in trenches adjacent to pillars, while word lines extend horizontally at different elevations, creating a nested spatial arrangement that maximizes connectivity without increasing planar footprint.
2Area of stationary object
If the wiring is made narrower to increase integration density, then the device area is reduced, but the wiring resistance becomes greater
Solution Approach 1:
Wiring structures extend into the vertical dimension, allowing current paths to be lengthened in the z-direction rather than compressing them in the planar x-y directions. This maintains effective conductivity while reducing the planar area occupied by interconnects.
Solution Approach 2:
Multiple wiring functions are combined into integrated three-dimensional structures where bit lines and word lines share vertical space through strategic positioning at different heights, reducing the total wiring volume required while maintaining low resistance pathways.
Data Source
AI summary
A semiconductor memory device includes first and second active pillar structures protruding at an upper part of a substrate, buried bit lines each extending in a first direction, and first gate patterns and second gate patterns each extending in a second direction. The first and second active pillar structures occupy odd-numbered and even-numbered rows, respectively. The first and the second active pillar structures also occupy even-numbered and odd-numbered columns, respectively. The columns of the second active pillar structures are offset in the second direction from the columns of the first active pillar structures. Each buried bit line is connected to lower portions of the first active pillar structures which occupy one of the even-numbered columns and to lower portions of the second active pillar structures which occupy an adjacent one of the odd-numbered columns.