Memory Plane Ramp Rate Control for Current Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing non-volatile memory devices face challenges in efficiently managing current consumption and programming speed due to varying voltage rates applied to bit lines and word lines during programming operations, which can exceed current limitations in host devices.
Innovation Solution
A memory apparatus and method that includes a control circuit to determine if all planes are involved in a program operation, adjusting the bit line ramp rate and word line ramp rate based on the number of program-verified planes, using default and shifted ramp rate lookup tables to optimize voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high voltage ramp rates are applied to bit lines and word lines during programming operations, then programming speed is improved, but current consumption exceeds host device limitations
Solution Approach 1:
The patent implements dynamic adjustment of voltage ramp rates based on the number of planes being programmed. The control circuit selectively applies different ramp rate profiles (first ramp rate for single-plane operations, second ramp rate for multi-plane operations) to optimize the balance between programming speed and current consumption, allowing the system to adapt its voltage application characteristics to operational conditions
Solution Approach 2:
The patent changes the voltage ramp rate parameter according to the programming operation scope. By modifying the ramp rate from a fixed value to a variable parameter that depends on the number of planes involved, the system can reduce current peaks when programming multiple planes while maintaining acceptable programming speed, thus resolving the contradiction between speed and energy usage
2Use of energy by moving object
If voltage ramp rates are reduced to comply with host device current limitations, then current consumption is controlled, but programming speed decreases
Solution Approach 1:
The control circuit dynamically selects between different voltage ramp rate profiles based on real-time operational conditions. When only one plane is being programmed, the system uses a faster ramp rate to maximize speed. When multiple planes are involved, it switches to a slower ramp rate to control current consumption, thus dynamically optimizing the trade-off between speed and energy usage
Solution Approach 2:
The patent modifies the voltage ramp rate parameter adaptively based on the number of planes being programmed. This parameter change allows the system to maintain high programming speed for single-plane operations while controlling current consumption for multi-plane operations, resolving the contradiction between speed and energy constraints
3Device complexity
If default voltage ramp rates are used for all programming operations, then device complexity is reduced, but performance is suboptimal when not all planes are utilized
Solution Approach 1:
The control circuit implements dynamic selection between different voltage ramp rate profiles based on the number of planes being programmed. The system monitors the programming operation scope and automatically adjusts the voltage application characteristics, achieving optimal performance without requiring complex manual configuration or fixed conservative settings
Solution Approach 2:
The patent changes the voltage ramp rate parameter based on operational conditions (number of planes). This adaptive parameter modification allows the system to achieve high programming efficiency when only one plane is involved while maintaining safe current levels for multi-plane operations, improving productivity without excessive complexity
Data Source
AI summary
A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in a plurality of planes. The apparatus also includes a control circuit coupled to the word lines and the bit lines and configured to determine whether a program operation of the memory cells involves all of the plurality of planes. In response to the program operation of the memory cells not involving all of the plurality of planes, the control circuit adjusts at least one of a bit line ramp rate of a bit line voltage applied to the bit lines and a word line ramp rate of at least one word line voltage applied to the word lines during the program operation based on a quantity of the plurality of planes associated with the memory cells being program-verified in the program operation.