Memory Power Management Circuit for Isolated Power Domain Switching

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Solution Overview

Problem

Integrated circuits (ICs) face challenges in reducing power consumption while maintaining proper functionality, particularly in memory circuits with multiple power domains, as existing power management schemes are not sufficiently flexible.

Innovation Solution

A power management circuit that controls supply voltages to memory circuits using independent power domains, enabling power mode transitions and isolating power domains through level shifters and latches to reduce power consumption, including the ability to turn off VDD during buck-off states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If power management circuits use independent power domains with level shifters and latches to enable flexible power mode transitions, then power consumption is reduced, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidcircuit complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The power management circuit is divided into multiple independent power domains (first power domain and second power domain), each capable of independent power mode control. This segmentation allows selective power management of different circuit blocks, reducing overall power consumption while maintaining functionality where needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Level shifters are introduced as intermediary components between power domains with different voltage levels. These level shifters enable safe signal transmission across power domain boundaries during power mode transitions, managing the complexity of voltage coordination while enabling flexible power management.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 3:

Latches are used to store and maintain power mode control signal states across power domain boundaries. This feedback mechanism ensures proper sequencing and coordination of power mode transitions, managing the complexity of synchronous operation while enabling reduced power consumption states.

Inventive Principle:
Principle #23Feedback

2Use of energy by moving object

If power domains are isolated using level shifters during buck-off states, then power consumption is reduced, but ease of operation deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoidpower mode transition control
Core Design Contradiction:
Use of energy by moving objectVSEase of operation

Solution Approach 1:

The system prepares for power domain isolation by establishing proper voltage level translation paths through level shifters before buck-off states occur. Control signals are pre-positioned in latches to maintain proper sequencing, making the isolation process automatic and transparent to higher-level control, thus maintaining ease of operation while reducing power consumption.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250226012A1Circuit and method for power management
Publication Date: 2025.07.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250226012A1 patent drawing
  • US20250226012A1 patent drawing
  • US20250226012A1 patent drawing

AI summary

A circuit includes a memory circuit, and a power management circuit having a first circuit. The first circuit is configured to, in response to a first state of the first power management control signal and a first state of the second power management control signal, control supply of a first supply voltage to the memory circuit in accordance with a first power mode control signal. The first circuit is further configured to, in response to a second state of the first power management control signal, store a state of the first power mode control signal, and control supply of the first supply voltage to the memory circuit in accordance with the stored state of the first power mode control signal. The power management circuit is configured to, in response to a second state of the second power management control signal, disable a part of the first circuit.