3D Semiconductor Memory Power Pad and Segmented Bit Line
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in stably providing operating voltages to peripheral circuit elements due to limited power transfer paths, which can lead to unreliable device performance.
Innovation Solution
The semiconductor memory device incorporates a power pad disposed between bit line sections over dummy blocks, creating additional power transfer paths by cutting bit lines, thereby securing sufficient power paths and ensuring stable voltage delivery to peripheral circuit elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are continuous over dummy blocks, then manufacturing process is simpler, but power transfer paths are insufficient leading to unstable operating voltage supply
Solution Approach 1:
The bit lines are segmented into first and second bit line sections that extend in opposite directions from both ends of the dummy block. This segmentation creates separate power transfer paths that allow power pads to be disposed between the sections, enabling sufficient power delivery to peripheral circuit elements while maintaining a manageable structural complexity through systematic arrangement.
2Reliability
If power pads are disposed between bit line sections, then power transfer paths are sufficient, but bit lines must be divided and routed around dummy blocks increasing structural complexity
Solution Approach 1:
The bit lines are extended into the third dimension by routing them over the dummy blocks in a vertical arrangement, with first and second bit line sections extending in opposite directions from both ends of the dummy block. This dimensional approach allows power pads to be disposed in the space between bit line sections, creating sufficient power transfer paths while organizing the complex layout in a systematic three-dimensional structure.
3Reliability
If bit lines extend continuously across the device, then manufacturing is easier, but power transfer paths are limited causing unstable peripheral circuit operation
Solution Approach 1:
The bit lines are divided into first and second bit line sections that extend in opposite directions from both ends of the dummy block, with power pads disposed between these sections. This segmentation creates multiple power transfer paths that ensure stable operation of peripheral circuit elements while maintaining manufacturing feasibility through a systematic division of the bit line structure into manageable sections.
Data Source
AI summary
A semiconductor memory device includes a logic structure including a peripheral circuit element which is formed over a substrate, a bottom dielectric layer which covers the peripheral circuit element and a bottom wiring line which is disposed in the bottom dielectric layer and is coupled to the peripheral circuit element; a memory structure stacked over the logic structure in a first direction perpendicular to a top surface of the substrate; a bit line disposed over a first top dielectric layer which covers the memory structure, extending in a second direction parallel to the top surface of the substrate, and divided into first and second bit line sections; and a power pad disposed over the first top dielectric layer between the first bit line section and the second bit line section, and coupled to the bottom wiring line through a power coupling contact which passes through the memory structure.