Memory Power-Up Test Register for ROM Verify Without Extra Area
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Solution Overview
Problem
The existing program verify scheme for anti-fuse memories requires a second data register, leading to increased circuit area and manufacturing costs due to complex logic for disabling successfully programmed bit positions and detecting failed programming.
Innovation Solution
A dual function serial and parallel data register with integrated program verify functionality that concurrently stores two different words of data, using master and slave latching circuits to compare data and automatically inhibit reprogramming of successfully programmed bits, thereby eliminating the need for a second data register.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a second data register is used for program verify operations, then program verification functionality is achieved, but circuit area and manufacturing cost increase due to complex logic requirements
Solution Approach 1:
The patent combines the program verify functionality with the existing data register by integrating master and slave latching circuits into a single register structure. The master latch stores program data while the slave latch stores read data, allowing both functions to coexist in one register unit rather than requiring separate registers. This merging eliminates the need for a second dedicated verify register, thereby reducing circuit area while maintaining full program verification capability.
Solution Approach 2:
The data register is designed to serve multiple functions: it can store program data, store read data, and perform program verify operations all within the same register structure. The master and slave latches work together to enable the register to handle both data storage and verification tasks, making the register universal rather than specialized for a single function. This multi-functionality reduces the overall circuit area by eliminating redundant dedicated verify circuitry.
2Measurement precision
If complex logic is implemented for disabling successfully programmed bit positions and detecting failed programming, then program verify accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements feedback mechanisms where the master and slave latches continuously compare their stored data values. The XOR gates compare corresponding bits from both latches, and the comparison results are fed back through AND gates to generate the final verify status. This feedback loop automatically detects programming failures and disables reprogramming of successfully programmed bits, achieving high verify accuracy through systematic feedback rather than complex combinatorial logic.
Solution Approach 2:
The verify logic is segmented into modular components distributed across multiple register stages. Each stage contains its own XOR gates for bit comparison and AND gates for result integration, breaking down the complex verify logic into manageable segments. This segmentation allows the system to achieve high verify accuracy through distributed modular logic rather than a single complex logic block, reducing overall device complexity while maintaining precision.
Data Source
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AI summary
The invention pertains to a power up test system (600) comprising: - a first row (Row 1) of ROM memory cells storing a first predetermined data word, each memory cell of the first row (Row 1) of ROM memory cells being connected to corresponding bitlines; - a second row (Row 2) of ROM memory cells storing a second predetermined data word, each memory cell of the second row (Row 2) of ROM memory cells being connected to the corresponding bitlines, and the second predetermined data word being a single bit shifted first predetermined data word; - sense amplifiers (606) coupled to the corresponding bitlines for sensing a first read word from the first row (Row 1) of ROM memory cells in a first read operation and for sensing a second read word from the second row (Row 2) of ROM memory cells in a second read operation; - a dual function data register (608) for receiving the first read word into master latches (662) and for shifting the first read word into slave latches (664) in the first read operation, the dual function data register (608) receiving the second read word into the master latches (662); and - a data comparison logic for comparing data between the master latches (662) and the slave latches (664), and for providing a signal indicating matching data between the master latches (662) and the slave latches (664).