Memory Pre-Decoder Biasing for Low-Power Polarity Switching
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Solution Overview
Problem
Existing memory devices using 1P1N bi-polar decoders exhibit significant power consumption due to changing gate biases during polarity transitions in memory cell configurations.
Innovation Solution
Utilizing decoder circuitry with two n-type transistors (2N bi-polar decoders) to provide selection and de-selection signals, which maintain static gate biases during polarity transitions, reducing power consumption and circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 1P1N bi-polar decoders are used to provide selection and de-selection signals, then the memory cells can be accessed with polarity transitions, but significant power consumption occurs due to changing gate biases during polarity transitions
Solution Approach 1:
The patent changes the fundamental parameter of the decoder architecture from 1P1N to 2N configuration, which fundamentally alters how gate biases are handled during polarity transitions. This parameter change eliminates the need for bias switching circuitry and maintains static gate biases, thereby resolving the power consumption issue while preserving memory access capability
Solution Approach 2:
The patent extracts and removes the bias switching circuitry that was present in 1P1N decoders from the 2N decoder architecture. By taking out this unnecessary component, the design eliminates the source of power consumption during polarity transitions while maintaining the essential selection and de-selection signal generation functionality
2Ease of operation
If 1P1N bi-polar decoders are used, then memory cell selection can be achieved, but circuit complexity increases due to bias switching requirements
Solution Approach 1:
The patent removes the bias switching circuitry from the decoder design by transitioning to a 2N configuration. This extraction of unnecessary components simplifies the overall circuit architecture while maintaining the ability to provide selection and de-selection signals for memory cell access
Solution Approach 2:
Instead of switching biases as in the conventional 1P1N approach, the patent inverts the approach by using a 2N configuration where gate biases remain static. This inversion of the bias switching paradigm fundamentally simplifies the circuit design and reduces complexity
Data Source
AI summary
The disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the array and comprising a first and second n-type transistor having a first and second gate, respectively, and pre-decoder circuitry to provide a bias condition for the first and second gate to provide a selection signal to one of the cells. The bias condition comprises a positive voltage for the first gate and a negative voltage for the second gate for a positive memory cell configuration, and zero volts for the first gate and the negative voltage for the second gate for a negative memory cell configuration. The pre-decoder circuitry comprises first pre-decoder circuitry to provide the positive voltage for the first gate and the zero volts for the second gate and second pre-decoder circuitry to provide the negative voltage for the second gate.