Memory Device Program Disturb Suppression via Recovery Phase Control
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Solution Overview
Problem
Program disturb occurs during the recovery phase of a program loop in memory devices, particularly due to source-side injection (SSI) type disturbances, which can lead to read errors and reduced write performance, especially when the risk factors such as temperature, program-erase cycles, and program pulse magnitude are high.
Innovation Solution
The duration of the recovery phase is extended when the risk of program disturb is greater, and the ramp down of voltages for the drain-side word line is made earlier than for the source-side word lines, or the bit line voltages of inhibited NAND strings are ramped down before the SGD voltage, and a lower recovery voltage is set for the source-side word lines compared to the drain-side word lines, to mitigate SSI program disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the recovery phase duration is extended to reduce program disturb, then write performance is improved, but program time increases
Solution Approach 1:
The patent applies dynamics by making the recovery phase duration variable rather than fixed. The control circuit dynamically adjusts the recovery phase duration based on detected risk factors (temperature, program-erase cycle count, program pulse magnitude) to extend the recovery phase only when program disturb risk is high, thereby resolving the contradiction between reliability improvement and time loss.
Solution Approach 2:
The patent changes the parameter of recovery phase duration based on multiple risk factors. By monitoring temperature, program-erase cycle count, and program pulse magnitude, the system adjusts the recovery phase duration parameter adaptively, extending it only when necessary to reduce program disturb, thus balancing reliability improvement with time efficiency.
2Reliability
If voltage ramp down timing is adjusted to mitigate SSI program disturb, then read errors are reduced, but control complexity increases
Solution Approach 1:
The patent applies preliminary action by having the control circuit detect risk factors before the program disturb occurs and adjust the voltage ramp down timing in advance. The system monitors temperature, program-erase cycle count, and program pulse magnitude, and proactively adjusts the drain-side word line voltage ramp down timing to prevent SSI program disturb before it happens, thereby reducing read errors while managing control complexity through systematic monitoring.
3Reliability
If recovery voltage for source-side word lines is reduced to prevent program disturb, then write performance is enhanced, but program uniformity becomes harder to maintain
Solution Approach 1:
The patent applies local quality by applying different recovery voltages to different groups of word lines based on their position and risk factors. The control circuit reduces the recovery voltage specifically for source-side word lines (WLn-1, WLn-2) while maintaining different voltages for drain-side word lines, creating localized voltage adjustments that target program disturb prevention in specific regions without compromising overall program uniformity.
Data Source
AI summary
Program disturb is suppressed during a program recovery phase of a program operation in a memory device. The duration of the recovery phase can be increased when the risk of program disturb is greater due to factors such as temperature, the position of the selected word line, the number of program-erase cycles and the program pulse magnitude. In other approaches, the risk of program disturb is reduced by providing an early ramp down of the voltages of the drain-side word line relative to a ramp down of the voltages of the source-side word lines, providing an early ramp down of the bit line voltage of the inhibited NAND strings relative to the ramp down of the select gate voltage or setting a lower recovery voltage for the source-side word lines relative to the recovery voltage of the drain-side word lines.