Memory Device Program Loop Parameter Segmentation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Flash memory devices experience errors due to unintended changes in threshold voltages of memory cells, leading to reliability issues, as these changes can occur due to various factors such as interference and environmental conditions.

Innovation Solution

An operation method for a memory device that involves performing multiple program loops with different program parameters, including varying program voltages and bit line forcing voltages, to maintain threshold voltages within a narrow range, thereby minimizing errors and enhancing reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple program loops with different program parameters are performed, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata retention reliabilityVSAvoidprogram operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The program operation is segmented into multiple program loops (first program loop, second program loop, third program loop) with different program parameters. Each loop targets specific threshold voltage ranges with optimized voltage increments and bit line forcing voltages, thereby improving reliability while managing complexity through structured segmentation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent dynamically adjusts program parameters including program voltage increments and bit line forcing voltages across different program loops based on the current threshold voltage distribution state. This dynamic adaptation allows the system to optimize programming precision for different voltage ranges, improving reliability without requiring a completely complex fixed-structure approach.

Inventive Principle:
Principle #15Dynamics

2Manufacturing precision

If program voltage increment is controlled in specific program loops, then manufacturing precision is improved, but loss of time increases

Engineering Contradiction:
Improvethreshold voltage control precisionVSAvoidprogram operation time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

Different program voltage increments are applied locally to different program loops based on the specific threshold voltage ranges being targeted. The first program loop uses a first program voltage increment for initial programming, while subsequent loops use different increments for fine-tuning specific voltage ranges, thereby achieving high precision without uniformly increasing operation time across all loops.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes program parameters including voltage increments and bit line forcing voltages between different program loops. By adjusting these parameters dynamically, the system achieves precise threshold voltage control in critical ranges while maintaining faster programming in less critical ranges, balancing precision requirements with time efficiency.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If bit line forcing voltage is varied in program loops, then reliability is improved, but use of energy increases

Engineering Contradiction:
Improvedata storage reliabilityVSAvoidenergy consumption during programming
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent employs periodic application of bit line forcing voltages in alternating program loops rather than continuous application. The first program loop applies a first bit line forcing voltage, followed by a second program loop with a second bit line forcing voltage, creating a periodic pattern that improves reliability through varied stress conditions while reducing overall energy consumption compared to sustained high-voltage application.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS12176046B2Operation method of memory device and operation method of memory system including the same
Publication Date: 2024.12.24 SAMSUNG ELECTRONICS CO LTD
  • US12176046B2 patent drawing
  • US12176046B2 patent drawing
  • US12176046B2 patent drawing

AI summary

Disclosed is an operation method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate. The method includes performing first to (n−1)-th program loops on selected memory cells connected to a selected word line from among the plurality of memory cells, based on a first program parameter, and after the (n−1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter. Herein, n is an integer greater than 1 and k is an integer greater than or equal to n. The first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.