Memory Cell Programming Sequence for Disturbance and Hot Carrier Control

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Solution Overview

Problem

The reliability of nonvolatile memory devices is compromised due to program disturbances and hot carrier injection during incremental step pulse programming, which affects the durability and efficiency of memory cells.

Innovation Solution

A memory device and programming method that includes applying a recovery voltage to word lines in specific sequences, activating string selection lines, and optimizing recovery periods to reduce program time and minimize negative boosting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If incremental step pulse programming (ISPP) is used to program memory cells, then programming precision is improved, but program disturbance and hot carrier injection occur causing reliability deterioration

Engineering Contradiction:
Improveprogramming precisionVSAvoiddevice reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent segments the word line recovery process into multiple distinct phases: a first recovery period where recovery voltage is applied to first word lines before bit line setup, and a second recovery period where recovery voltage is applied to second word lines after bit line setup. This segmentation allows precise control over when different word lines are recovered, preventing program disturbance while maintaining programming precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies recovery voltage to certain word lines (first word lines) in advance, before the bit line setup operation commences. This preliminary recovery action prevents negative boosting and program disturbance on those word lines before they can be affected by the programming operation, thereby maintaining reliability while enabling precise ISPP programming.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If recovery operation is performed on all word lines before bit line setup, then program disturbance is reduced, but program time increases

Engineering Contradiction:
Improveprogram stabilityVSAvoidprogram time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides word lines into two groups (first word lines and second word lines) and recovers them at different times relative to the bit line setup operation. First word lines are recovered before bit line setup, while second word lines are recovered after bit line setup. This segmentation eliminates the need to wait for all word lines to be recovered before proceeding, thereby reducing program time while still protecting against program disturbance on the first word lines.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies recovery voltage to only certain word lines (first word lines) before the bit line setup operation, rather than waiting to recover all word lines. This partial recovery action is sufficient to prevent program disturbance on the critical first word lines, allowing the bit line setup to proceed without delay and thus reducing overall program time.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If string selection lines are activated later in the programming sequence, then program disturbance is minimized, but setup time increases

Engineering Contradiction:
Improveprogram accuracyVSAvoidsetup time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies recovery voltage to first word lines as a preliminary action before initiating the bit line setup operation. This ensures that these word lines are recovered and ready before the string selection lines are activated and the programming operation begins, preventing program disturbance without delaying the overall timing sequence.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20260045309A1Memory device and programming method of memory device
Publication Date: 2026.02.12 SAMSUNG ELECTRONICS CO LTD
  • US20260045309A1 patent drawing
  • US20260045309A1 patent drawing
  • US20260045309A1 patent drawing

AI summary

Semiconductor devices and methods for operating the semiconductor devices are provided. In one aspect, a memory device includes a plurality of memory cells connected to a plurality of word lines including a first group of word lines and a second group of word lines; and a control logic. The control logic is configured to: in a bit line setup period, perform a setup operation of applying a string selection line voltage to string selection lines connected to at least one of the cell strings to activate the string selection lines; in a first recovery period before the setup operation is performed, apply a first recovery voltage to the first group of word lines; and in a second recovery period after the first recovery period, apply a second recovery voltage to the second group of word lines