Memory Programming Using Coarse Step Size and Error Storage
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Solution Overview
Problem
Existing memory devices face challenges in achieving high-speed programming of analog memory cells while maintaining accuracy and reducing wear and program disturb interference, particularly in Multi-Level Cell (MLC) devices, where coarse programming accuracy degrades performance and increases error probabilities.
Innovation Solution
The method involves dividing the memory cell array into a data storage area and an error storage area, using a coarse Program and Verify (P&V) step size for fast programming, measuring residual errors, and storing error information in the error storage area to reconstruct data with high accuracy, thereby improving trade-offs between programming speed and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a coarse Program and Verify (P&V) step size is used for fast programming, then programming speed is improved, but programming accuracy deteriorates
Solution Approach 1:
The patent segments the programming process into two distinct phases: a first fast programming phase using coarse P&V step size to achieve high speed, and a second refinement phase using fine P&V step size to achieve high accuracy. This segmentation allows each phase to be optimized for its specific purpose without compromising the other.
Solution Approach 2:
The patent performs preliminary fast programming using coarse step size to bring the memory cell values close to the target state before performing the refinement phase. This preliminary action reduces the total number of iterations needed in the subsequent fine-tuning phase, thereby improving overall programming speed while maintaining accuracy.
2Loss of time
If a coarse Program and Verify (P&V) step size is used, then programming time is reduced, but error probability increases
Solution Approach 1:
The patent divides the programming operation into a first operation with coarse step size (reducing time) and a second operation with fine step size (reducing errors). This segmentation ensures that the time-consuming fine programming is performed only when necessary to correct errors introduced by the coarse programming phase.
Solution Approach 2:
The patent implements a feedback mechanism where the results of the first fast programming phase are evaluated, and based on this evaluation, the second refinement phase is selectively applied to correct any errors or inaccuracies. This feedback loop ensures high reliability while minimizing total programming time.
3Productivity
If a coarse Program and Verify (P&V) step size is used, then programming speed is improved, but wear and program disturb interference increase
Solution Approach 1:
The patent segments the programming process to perform the majority of the programming work in the first phase using coarse step size, which minimizes the number of programming pulses and reduces wear. The second phase uses fine step size only when necessary, further reducing unnecessary wear from excessive fine programming operations.
Solution Approach 2:
The patent applies partial fine programming only when and where needed, rather than applying fine step size to all cells throughout the entire programming process. This selective approach reduces the total number of programming pulses applied, thereby reducing wear and program disturb interference while maintaining programming accuracy.
Data Source
AI summary
A method for operating a memory that includes a plurality of analog memory cells includes storing data in a first group of the memory cells by writing respective first cell values to the memory cells in the first group. After storing the data, respective second cell values are read from the memory cells in the first group, and differences are found between the respective first and second cell values for each of one or more of the memory cells in the first group. The differences are processed to produce error information, and the error information is stored in a second group of the memory cells.