Memory Device Programming Segmentation for Stable Upper States
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Solution Overview
Problem
Existing memory devices face challenges in efficiently performing program operations across a wide range of program states, particularly in maintaining data reliability and stability of upper program states.
Innovation Solution
The memory device employs a peripheral circuit that performs a first program voltage application operation on initial memory cells, followed by a pre-program voltage application operation on secondary memory cells, and includes data conversion operations in parallel with voltage application processes to optimize program state transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single program voltage application operation is performed on all memory cells, then the program operation is simple and fast, but the stability and reliability of upper program states deteriorates
Solution Approach 1:
The program voltage application operation is divided into two distinct segments: a first program voltage application operation for first memory cells and a second program voltage application operation for second memory cells. This segmentation allows different voltage levels and timing to be applied to different groups of memory cells, thereby improving the stability of upper program states while maintaining manageable operational complexity through systematic organization.
Solution Approach 2:
The first program voltage application operation is performed as a preliminary action before the second program voltage application operation. By pre-programming certain memory cells with appropriate voltage levels and states beforehand, the subsequent operations can proceed more efficiently with improved reliability, as the foundation for stable upper program states is established in advance.
2Productivity
If program operations are performed sequentially on all memory cells, then data reliability is maintained, but total program time increases
Solution Approach 1:
The memory cells are segmented into first memory cells and second memory cells, allowing parallel or overlapping program operations to be performed on different segments. This reduces total program time while maintaining data reliability through differentiated voltage application strategies for each segment.
Solution Approach 2:
The patent implements continuous useful action by performing the first program voltage application operation and the second program voltage application operation in an overlapping or continuous manner rather than strictly sequentially. This ensures that program operations proceed without idle time while maintaining data integrity through appropriate voltage management.
3Reliability
If pre-program voltage application operation is performed after first program voltage application operation, then program state transitions become more reliable, but program time increases
Solution Approach 1:
The first program voltage application operation serves as a preliminary action that prepares memory cells for the subsequent second program voltage application operation. By establishing initial program states with the first operation, the second operation can proceed more efficiently with improved transition reliability, reducing the overall time penalty.
Solution Approach 2:
The patent employs dynamic voltage application strategies where the timing, duration, and magnitude of program voltages are adjusted based on the state of memory cells and the desired program state transitions. This dynamic approach optimizes the balance between transition reliability and program time by applying voltages only when and where needed.
Data Source
AI summary
A memory device includes a plurality of memory cells, where each memory cell is configured to be in an erased state or one of a plurality of program states according to data stored therein. The memory device also includes a peripheral circuit configured to, in a program operation on the plurality of memory cells, perform a first program voltage application operation on first memory cells, the first memory cells being to be programmed to first respective program states. The peripheral circuit is also configured to perform, after the first program voltage application operation, a pre-program voltage application operation on second memory cells, the second memory cells being to be programmed to second respective program states.